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Searched refs:wait_for (Results 1 – 18 of 18) sorted by relevance

/drivers/mmc/host/
Dsh_mmcif.c239 enum mmcif_wait_for wait_for; member
527 host->state, host->wait_for); in sh_mmcif_error_manage()
531 host->state, host->wait_for); in sh_mmcif_error_manage()
535 host->state, host->wait_for); in sh_mmcif_error_manage()
567 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
590 host->wait_for = MMCIF_WAIT_FOR_READ_END; in sh_mmcif_read_block()
606 host->wait_for = MMCIF_WAIT_FOR_MREAD; in sh_mmcif_multi_read()
645 host->wait_for = MMCIF_WAIT_FOR_WRITE; in sh_mmcif_single_write()
668 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; in sh_mmcif_write_block()
684 host->wait_for = MMCIF_WAIT_FOR_MWRITE; in sh_mmcif_multi_write()
[all …]
/drivers/gpu/drm/gma500/
Dintel_gmbus.c51 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
279 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) in gmbus_xfer()
307 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) in gmbus_xfer()
322 …if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), … in gmbus_xfer()
Dcdv_intel_display.c171 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
190 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
213 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
226 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
Dcdv_intel_dp.c52 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
235 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
269 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { in cdv_intel_edp_panel_off()
/drivers/gpu/drm/i915/
Di915_drv.c786 ret = wait_for(i965_reset_complete(dev), 500); in i965_do_reset()
796 return wait_for(i965_reset_complete(dev), 500); in i965_do_reset()
809 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); in ironlake_do_reset()
818 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); in ironlake_do_reset()
841 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); in gen6_do_reset()
Dintel_crt.c276 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in intel_ironlake_crt_detect_hotplug()
313 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in valleyview_crt_detect_hotplug()
372 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & in intel_crt_detect_hotplug()
Dintel_lvds.c199 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) in intel_enable_lvds()
223 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) in intel_disable_lvds()
Dintel_pm.c69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { in i8xx_disable_fbc()
2769 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), in ironlake_disable_rc6()
4151 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & in intel_set_power_well()
4536 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, in sandybridge_pcode_read()
4560 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, in sandybridge_pcode_write()
4599 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, in vlv_punit_rw()
Dintel_display.c905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) in ironlake_wait_for_vblank()
944 if (wait_for(I915_READ(pipestat_reg) & in intel_wait_for_vblank()
977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, in intel_wait_for_pipe_off()
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_write()
1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_write()
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_read()
1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_read()
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) in ironlake_enable_pch_transcoder()
1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) in lpt_enable_pch_transcoder()
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) in ironlake_disable_pch_transcoder()
[all …]
Dintel_i2c.c261 return wait_for(C, 10); in gmbus_wait_idle()
Dintel_drv.h62 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
Dintel_ringbuffer.c409 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && in init_ring_common()
1533 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & in gen6_bsd_ring_write_tail()
Di915_dma.c790 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) in i915_wait_irq()
Dintel_dp.c1818 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), in intel_dp_set_idle_link_train()
Di915_gem.c4044 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) in i915_gem_init()
/drivers/gpu/drm/exynos/
Dexynos_drm_drv.h37 #define wait_for(COND, MS) _wait_for(COND, MS) macro
/drivers/staging/comedi/drivers/
Ddt282x.c262 #define wait_for(a, b) \ macro
567 wait_for(!mux_busy(), comedi_error(dev, "timeout\n"); return -ETIME;); in dt282x_ai_insn_read()
572 wait_for(ad_done(), comedi_error(dev, "timeout\n"); in dt282x_ai_insn_read()
707 wait_for(!mux_busy(), comedi_error(dev, "timeout\n"); return -ETIME;); in dt282x_ai_cmd()
/drivers/scsi/
Dscsi_lib.c1482 unsigned long wait_for = (cmd->allowed + 1) * rq->timeout; in scsi_softirq_done() local
1493 time_before(cmd->jiffies_at_alloc + wait_for, jiffies)) { in scsi_softirq_done()
1496 wait_for/HZ); in scsi_softirq_done()