Home
last modified time | relevance | path

Searched refs:wr32 (Results 1 – 25 of 57) sorted by relevance

123

/drivers/net/ethernet/intel/igb/
Digb_ptp.c143 wr32(E1000_SYSTIML, ts->tv_nsec); in igb_ptp_write_i210()
144 wr32(E1000_SYSTIMH, ts->tv_sec); in igb_ptp_write_i210()
222 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); in igb_ptp_adjfreq_82576()
248 wr32(E1000_TIMINCA, inca); in igb_ptp_adjfreq_82580()
654 wr32(E1000_RXPBS, regval); in igb_ptp_hwtstamp_ioctl()
662 wr32(E1000_TSYNCTXCTL, regval); in igb_ptp_hwtstamp_ioctl()
668 wr32(E1000_TSYNCRXCTL, regval); in igb_ptp_hwtstamp_ioctl()
671 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); in igb_ptp_hwtstamp_ioctl()
675 wr32(E1000_ETQF(3), in igb_ptp_hwtstamp_ioctl()
680 wr32(E1000_ETQF(3), 0); in igb_ptp_hwtstamp_ioctl()
[all …]
De1000_82575.c143 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_init_phy_params_82575()
674 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); in igb_get_phy_id_82575()
706 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_get_phy_id_82575()
856 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d0_lplu_state_82580()
901 wr32(E1000_82580_PHY_POWER_MGMT, data); in igb_set_d3_lplu_state_82580()
985 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_82575()
1010 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_82575()
1107 wr32(E1000_PCS_CFG0, reg); in igb_power_up_serdes_link_82575()
1112 wr32(E1000_CTRL_EXT, reg); in igb_power_up_serdes_link_82575()
1191 wr32(E1000_PCS_CFG0, reg); in igb_shutdown_serdes_link_82575()
[all …]
Digb_main.c608 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_data()
633 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_clk()
883 wr32(E1000_CTRL_EXT, tmp); in igb_configure_msix()
900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | in igb_configure_msix()
908 wr32(E1000_IVAR_MISC, tmp); in igb_configure_msix()
1119 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_set_interrupt_capability()
1436 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1437 wr32(E1000_EIMC, adapter->eims_enable_mask); in igb_irq_disable()
1439 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1442 wr32(E1000_IAM, 0); in igb_irq_disable()
[all …]
De1000_mac.c327 wr32(E1000_RAL(index), rar_low); in igb_rar_set()
329 wr32(E1000_RAH(index), rar_high); in igb_rar_set()
635 wr32(E1000_FCT, FLOW_CONTROL_TYPE); in igb_setup_link()
636 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igb_setup_link()
637 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igb_setup_link()
639 wr32(E1000_FCTTV, hw->fc.pause_time); in igb_setup_link()
665 wr32(E1000_TCTL, tctl); in igb_config_collision_dist()
699 wr32(E1000_FCRTL, fcrtl); in igb_set_fc_watermarks()
700 wr32(E1000_FCRTH, fcrth); in igb_set_fc_watermarks()
801 wr32(E1000_CTRL, ctrl); in igb_force_mac_fc()
[all …]
De1000_nvm.c44 wr32(E1000_EECD, *eecd); in igb_raise_eec_clk()
59 wr32(E1000_EECD, *eecd); in igb_lower_eec_clk()
90 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
102 wr32(E1000_EECD, eecd); in igb_shift_out_eec_bits()
189 wr32(E1000_EECD, eecd | E1000_EECD_REQ); in igb_acquire_nvm()
202 wr32(E1000_EECD, eecd); in igb_acquire_nvm()
224 wr32(E1000_EECD, eecd); in igb_standby_nvm()
228 wr32(E1000_EECD, eecd); in igb_standby_nvm()
266 wr32(E1000_EECD, eecd); in igb_release_nvm()
287 wr32(E1000_EECD, eecd); in igb_ready_nvm_eeprom()
[all …]
De1000_mbx.c253 wr32(E1000_MBVFICR, mask); in igb_check_for_bit_pf()
311 wr32(E1000_VFLRE, (1 << vf_number)); in igb_check_for_rst_pf()
331 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU); in igb_obtain_mbx_lock_pf()
370 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS); in igb_write_mbx_pf()
407 wr32(E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK); in igb_read_mbx_pf()
Digb_ethtool.c1198 wr32(reg, (_test[pat] & write)); in reg_pattern_test()
1217 wr32(reg, write & mask); in reg_set_and_check()
1281 wr32(E1000_STATUS, toggle); in igb_reg_test()
1291 wr32(E1000_STATUS, before); in igb_reg_test()
1398 wr32(E1000_IMC, ~0); in igb_intr_test()
1442 wr32(E1000_ICR, ~0); in igb_intr_test()
1444 wr32(E1000_IMC, mask); in igb_intr_test()
1445 wr32(E1000_ICS, mask); in igb_intr_test()
1464 wr32(E1000_ICR, ~0); in igb_intr_test()
1466 wr32(E1000_IMS, mask); in igb_intr_test()
[all …]
De1000_i210.c86 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); in igb_get_hw_semaphore_i210()
170 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_acquire_swfw_sync_i210()
194 wr32(E1000_SW_FW_SYNC, swfw_sync); in igb_release_swfw_sync_i210()
272 wr32(E1000_SRWR, eewr); in igb_write_nvm_srwr()
680 wr32(E1000_EECD, flup); in igb_update_flash_i210()
/drivers/gpu/drm/nouveau/core/engine/copy/
Dnvc0.c65 .wr32 = _nouveau_falcon_context_wr32,
163 .wr32 = _nouveau_falcon_wr32,
176 .wr32 = _nouveau_falcon_wr32,
Dnva3.c65 .wr32 = _nouveau_falcon_context_wr32,
162 .wr32 = _nouveau_falcon_wr32,
/drivers/gpu/drm/nouveau/core/engine/bsp/
Dnve0.c56 .wr32 = _nouveau_falcon_context_wr32,
108 .wr32 = _nouveau_falcon_wr32,
Dnvc0.c56 .wr32 = _nouveau_falcon_context_wr32,
108 .wr32 = _nouveau_falcon_wr32,
/drivers/gpu/drm/nouveau/core/engine/vp/
Dnvc0.c56 .wr32 = _nouveau_falcon_context_wr32,
108 .wr32 = _nouveau_falcon_wr32,
Dnve0.c56 .wr32 = _nouveau_falcon_context_wr32,
108 .wr32 = _nouveau_falcon_wr32,
Dnv84.c56 .wr32 = _nouveau_engctx_wr32,
/drivers/gpu/drm/nouveau/core/engine/ppp/
Dnvc0.c56 .wr32 = _nouveau_falcon_context_wr32,
108 .wr32 = _nouveau_falcon_wr32,
Dnv98.c61 .wr32 = _nouveau_engctx_wr32,
/drivers/gpu/drm/nouveau/core/engine/crypt/
Dnv98.c67 .wr32 = _nouveau_falcon_context_wr32,
163 .wr32 = _nouveau_falcon_wr32,
Dnv84.c74 .wr32 = _nouveau_gpuobj_wr32,
96 .wr32 = _nouveau_engctx_wr32,
/drivers/gpu/drm/nouveau/core/engine/fifo/
Dnv10.c104 .wr32 = _nouveau_fifo_channel_wr32,
126 .wr32 = _nouveau_fifo_context_wr32,
Dnv17.c111 .wr32 = _nouveau_fifo_channel_wr32,
133 .wr32 = _nouveau_fifo_context_wr32,
Dnv84.c302 .wr32 = _nouveau_fifo_channel_wr32,
312 .wr32 = _nouveau_fifo_channel_wr32,
377 .wr32 = _nouveau_fifo_context_wr32,
/drivers/gpu/drm/nouveau/core/engine/mpeg/
Dnv50.c76 .wr32 = _nouveau_gpuobj_wr32,
120 .wr32 = _nouveau_mpeg_context_wr32,
/drivers/gpu/drm/nouveau/core/subdev/instmem/
Dnv04.c87 .wr32 = nv04_instobj_wr32,
188 .wr32 = nv04_instmem_wr32,
/drivers/gpu/drm/nouveau/core/include/core/
Dobject.h93 void (*wr32)(struct nouveau_object *, u64 offset, u32 data); member
177 nv_ofuncs(obj)->wr32(obj, addr, data); in nv_wo32()

123