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Searched refs:wr_mid (Results 1 – 5 of 5) sorted by relevance

/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_uld.h57 (w)->wr.wr_mid = htonl(FW_WR_LEN16(DIV_ROUND_UP(sizeof(*w), 16)) | \
69 (w)->wr.wr_mid = htonl(FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \
Dsge.c974 u32 wr_mid; in t4_eth_xmit() local
1020 wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2)); in t4_eth_xmit()
1023 wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ; in t4_eth_xmit()
1027 wr->equiq_to_len16 = htonl(wr_mid); in t4_eth_xmit()
Dt4_msg.h194 __be32 wr_mid; member
/drivers/net/ethernet/chelsio/cxgb4vf/
Dsge.c1078 u32 wr_mid; in t4vf_eth_xmit() local
1152 wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2)); in t4vf_eth_xmit()
1164 wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ; in t4vf_eth_xmit()
1175 wr->equiq_to_len16 = cpu_to_be32(wr_mid); in t4vf_eth_xmit()
/drivers/infiniband/hw/cxgb4/
Dmem.c80 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); in _c4iw_write_mem_dma_aligned()
143 req->wr.wr_mid = cpu_to_be32( in _c4iw_write_mem_inline()