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Searched refs:wr_regl (Results 1 – 6 of 6) sorted by relevance

/drivers/tty/serial/
Dsirfsoc_uart.c136 wr_regl(port, SIRFUART_AFC_CTRL, val); in sirfsoc_uart_set_mctrl()
144 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_TX_INT_EN); in sirfsoc_uart_stop_tx()
152 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_START); in sirfsoc_uart_start_tx()
154 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_TX_INT_EN); in sirfsoc_uart_start_tx()
160 wr_regl(port, SIRFUART_RX_FIFO_OP, 0); in sirfsoc_uart_stop_rx()
162 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_RX_IO_INT_EN); in sirfsoc_uart_stop_rx()
173 wr_regl(port, SIRFUART_AFC_CTRL, reg & ~0x3FF); in sirfsoc_uart_disable_ms()
175 wr_regl(port, SIRFUART_INT_EN, reg & ~SIRFUART_CTS_INT_EN); in sirfsoc_uart_disable_ms()
187 wr_regl(port, SIRFUART_AFC_CTRL, reg | flg); in sirfsoc_uart_enable_ms()
189 wr_regl(port, SIRFUART_INT_EN, reg | SIRFUART_CTS_INT_EN); in sirfsoc_uart_enable_ms()
[all …]
Dsamsung.c110 wr_regl(port, S3C2410_UFCON, ufcon); in s3c24xx_serial_rx_enable()
114 wr_regl(port, S3C2410_UCON, ucon); in s3c24xx_serial_rx_enable()
129 wr_regl(port, S3C2410_UCON, ucon); in s3c24xx_serial_rx_disable()
250 wr_regl(port, S3C2410_UFCON, ufcon); in s3c24xx_serial_rx_chars()
368 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); in s3c64xx_serial_handle_irq()
372 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); in s3c64xx_serial_handle_irq()
424 wr_regl(port, S3C2410_UCON, ucon); in s3c24xx_serial_break_ctl()
451 wr_regl(port, S3C64XX_UINTP, 0xf); in s3c24xx_serial_shutdown()
452 wr_regl(port, S3C64XX_UINTM, 0xf); in s3c24xx_serial_shutdown()
510 wr_regl(port, S3C64XX_UINTM, 0xf); in s3c64xx_serial_startup()
[all …]
Dsamsung.h77 #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) macro
Dsirfsoc_uart.h177 #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) macro
/drivers/atm/
Dhorizon.c370 static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) { in wr_regl() function
399 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); in wr_mem()
400 wr_regl (dev, MEMORY_PORT_OFF, data); in wr_mem()
405 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); in rd_mem()
410 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000); in wr_framer()
411 wr_regl (dev, MEMORY_PORT_OFF, data); in wr_framer()
415 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000); in rd_framer()
448 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel); in SELECT_TX_CHANNEL()
966 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_schedule()
1049 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_schedule()
[all …]
Dhorizon.h493 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
495 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
497 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
499 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)