1 /* 2 * Performance events: 3 * 4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 7 * 8 * Data type definitions, declarations, prototypes. 9 * 10 * Started by: Thomas Gleixner and Ingo Molnar 11 * 12 * For licencing details see kernel-base/COPYING 13 */ 14 #ifndef _UAPI_LINUX_PERF_EVENT_H 15 #define _UAPI_LINUX_PERF_EVENT_H 16 17 #include <linux/types.h> 18 #include <linux/ioctl.h> 19 #include <asm/byteorder.h> 20 21 /* 22 * User-space ABI bits: 23 */ 24 25 /* 26 * attr.type 27 */ 28 enum perf_type_id { 29 PERF_TYPE_HARDWARE = 0, 30 PERF_TYPE_SOFTWARE = 1, 31 PERF_TYPE_TRACEPOINT = 2, 32 PERF_TYPE_HW_CACHE = 3, 33 PERF_TYPE_RAW = 4, 34 PERF_TYPE_BREAKPOINT = 5, 35 36 PERF_TYPE_MAX, /* non-ABI */ 37 }; 38 39 /* 40 * Generalized performance event event_id types, used by the 41 * attr.event_id parameter of the sys_perf_event_open() 42 * syscall: 43 */ 44 enum perf_hw_id { 45 /* 46 * Common hardware events, generalized by the kernel: 47 */ 48 PERF_COUNT_HW_CPU_CYCLES = 0, 49 PERF_COUNT_HW_INSTRUCTIONS = 1, 50 PERF_COUNT_HW_CACHE_REFERENCES = 2, 51 PERF_COUNT_HW_CACHE_MISSES = 3, 52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 53 PERF_COUNT_HW_BRANCH_MISSES = 5, 54 PERF_COUNT_HW_BUS_CYCLES = 6, 55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 57 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 58 59 PERF_COUNT_HW_MAX, /* non-ABI */ 60 }; 61 62 /* 63 * Generalized hardware cache events: 64 * 65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 66 * { read, write, prefetch } x 67 * { accesses, misses } 68 */ 69 enum perf_hw_cache_id { 70 PERF_COUNT_HW_CACHE_L1D = 0, 71 PERF_COUNT_HW_CACHE_L1I = 1, 72 PERF_COUNT_HW_CACHE_LL = 2, 73 PERF_COUNT_HW_CACHE_DTLB = 3, 74 PERF_COUNT_HW_CACHE_ITLB = 4, 75 PERF_COUNT_HW_CACHE_BPU = 5, 76 PERF_COUNT_HW_CACHE_NODE = 6, 77 78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 79 }; 80 81 enum perf_hw_cache_op_id { 82 PERF_COUNT_HW_CACHE_OP_READ = 0, 83 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 85 86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 87 }; 88 89 enum perf_hw_cache_op_result_id { 90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 92 93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 94 }; 95 96 /* 97 * Special "software" events provided by the kernel, even if the hardware 98 * does not support performance events. These events measure various 99 * physical and sw events of the kernel (and allow the profiling of them as 100 * well): 101 */ 102 enum perf_sw_ids { 103 PERF_COUNT_SW_CPU_CLOCK = 0, 104 PERF_COUNT_SW_TASK_CLOCK = 1, 105 PERF_COUNT_SW_PAGE_FAULTS = 2, 106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 107 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 111 PERF_COUNT_SW_EMULATION_FAULTS = 8, 112 113 PERF_COUNT_SW_MAX, /* non-ABI */ 114 }; 115 116 /* 117 * Bits that can be set in attr.sample_type to request information 118 * in the overflow packets. 119 */ 120 enum perf_event_sample_format { 121 PERF_SAMPLE_IP = 1U << 0, 122 PERF_SAMPLE_TID = 1U << 1, 123 PERF_SAMPLE_TIME = 1U << 2, 124 PERF_SAMPLE_ADDR = 1U << 3, 125 PERF_SAMPLE_READ = 1U << 4, 126 PERF_SAMPLE_CALLCHAIN = 1U << 5, 127 PERF_SAMPLE_ID = 1U << 6, 128 PERF_SAMPLE_CPU = 1U << 7, 129 PERF_SAMPLE_PERIOD = 1U << 8, 130 PERF_SAMPLE_STREAM_ID = 1U << 9, 131 PERF_SAMPLE_RAW = 1U << 10, 132 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 133 PERF_SAMPLE_REGS_USER = 1U << 12, 134 PERF_SAMPLE_STACK_USER = 1U << 13, 135 PERF_SAMPLE_WEIGHT = 1U << 14, 136 PERF_SAMPLE_DATA_SRC = 1U << 15, 137 138 PERF_SAMPLE_MAX = 1U << 16, /* non-ABI */ 139 }; 140 141 /* 142 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 143 * 144 * If the user does not pass priv level information via branch_sample_type, 145 * the kernel uses the event's priv level. Branch and event priv levels do 146 * not have to match. Branch priv level is checked for permissions. 147 * 148 * The branch types can be combined, however BRANCH_ANY covers all types 149 * of branches and therefore it supersedes all the other types. 150 */ 151 enum perf_branch_sample_type { 152 PERF_SAMPLE_BRANCH_USER = 1U << 0, /* user branches */ 153 PERF_SAMPLE_BRANCH_KERNEL = 1U << 1, /* kernel branches */ 154 PERF_SAMPLE_BRANCH_HV = 1U << 2, /* hypervisor branches */ 155 156 PERF_SAMPLE_BRANCH_ANY = 1U << 3, /* any branch types */ 157 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << 4, /* any call branch */ 158 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << 5, /* any return branch */ 159 PERF_SAMPLE_BRANCH_IND_CALL = 1U << 6, /* indirect calls */ 160 161 PERF_SAMPLE_BRANCH_MAX = 1U << 7, /* non-ABI */ 162 }; 163 164 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 165 (PERF_SAMPLE_BRANCH_USER|\ 166 PERF_SAMPLE_BRANCH_KERNEL|\ 167 PERF_SAMPLE_BRANCH_HV) 168 169 /* 170 * Values to determine ABI of the registers dump. 171 */ 172 enum perf_sample_regs_abi { 173 PERF_SAMPLE_REGS_ABI_NONE = 0, 174 PERF_SAMPLE_REGS_ABI_32 = 1, 175 PERF_SAMPLE_REGS_ABI_64 = 2, 176 }; 177 178 /* 179 * The format of the data returned by read() on a perf event fd, 180 * as specified by attr.read_format: 181 * 182 * struct read_format { 183 * { u64 value; 184 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 185 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 186 * { u64 id; } && PERF_FORMAT_ID 187 * } && !PERF_FORMAT_GROUP 188 * 189 * { u64 nr; 190 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 191 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 192 * { u64 value; 193 * { u64 id; } && PERF_FORMAT_ID 194 * } cntr[nr]; 195 * } && PERF_FORMAT_GROUP 196 * }; 197 */ 198 enum perf_event_read_format { 199 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 200 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 201 PERF_FORMAT_ID = 1U << 2, 202 PERF_FORMAT_GROUP = 1U << 3, 203 204 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ 205 }; 206 207 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 208 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 209 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 210 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 211 /* add: sample_stack_user */ 212 213 /* 214 * Hardware event_id to monitor via a performance monitoring event: 215 */ 216 struct perf_event_attr { 217 218 /* 219 * Major type: hardware/software/tracepoint/etc. 220 */ 221 __u32 type; 222 223 /* 224 * Size of the attr structure, for fwd/bwd compat. 225 */ 226 __u32 size; 227 228 /* 229 * Type specific configuration information. 230 */ 231 __u64 config; 232 233 union { 234 __u64 sample_period; 235 __u64 sample_freq; 236 }; 237 238 __u64 sample_type; 239 __u64 read_format; 240 241 __u64 disabled : 1, /* off by default */ 242 inherit : 1, /* children inherit it */ 243 pinned : 1, /* must always be on PMU */ 244 exclusive : 1, /* only group on PMU */ 245 exclude_user : 1, /* don't count user */ 246 exclude_kernel : 1, /* ditto kernel */ 247 exclude_hv : 1, /* ditto hypervisor */ 248 exclude_idle : 1, /* don't count when idle */ 249 mmap : 1, /* include mmap data */ 250 comm : 1, /* include comm data */ 251 freq : 1, /* use freq, not period */ 252 inherit_stat : 1, /* per task counts */ 253 enable_on_exec : 1, /* next exec enables */ 254 task : 1, /* trace fork/exit */ 255 watermark : 1, /* wakeup_watermark */ 256 /* 257 * precise_ip: 258 * 259 * 0 - SAMPLE_IP can have arbitrary skid 260 * 1 - SAMPLE_IP must have constant skid 261 * 2 - SAMPLE_IP requested to have 0 skid 262 * 3 - SAMPLE_IP must have 0 skid 263 * 264 * See also PERF_RECORD_MISC_EXACT_IP 265 */ 266 precise_ip : 2, /* skid constraint */ 267 mmap_data : 1, /* non-exec mmap data */ 268 sample_id_all : 1, /* sample_type all events */ 269 270 exclude_host : 1, /* don't count in host */ 271 exclude_guest : 1, /* don't count in guest */ 272 273 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 274 exclude_callchain_user : 1, /* exclude user callchains */ 275 276 __reserved_1 : 41; 277 278 union { 279 __u32 wakeup_events; /* wakeup every n events */ 280 __u32 wakeup_watermark; /* bytes before wakeup */ 281 }; 282 283 __u32 bp_type; 284 union { 285 __u64 bp_addr; 286 __u64 config1; /* extension of config */ 287 }; 288 union { 289 __u64 bp_len; 290 __u64 config2; /* extension of config1 */ 291 }; 292 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 293 294 /* 295 * Defines set of user regs to dump on samples. 296 * See asm/perf_regs.h for details. 297 */ 298 __u64 sample_regs_user; 299 300 /* 301 * Defines size of the user stack to dump on samples. 302 */ 303 __u32 sample_stack_user; 304 305 /* Align to u64. */ 306 __u32 __reserved_2; 307 }; 308 309 #define perf_flags(attr) (*(&(attr)->read_format + 1)) 310 311 /* 312 * Ioctls that can be done on a perf event fd: 313 */ 314 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 315 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 316 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 317 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 318 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 319 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 320 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 321 322 enum perf_event_ioc_flags { 323 PERF_IOC_FLAG_GROUP = 1U << 0, 324 }; 325 326 /* 327 * Structure of the page that can be mapped via mmap 328 */ 329 struct perf_event_mmap_page { 330 __u32 version; /* version number of this structure */ 331 __u32 compat_version; /* lowest version this is compat with */ 332 333 /* 334 * Bits needed to read the hw events in user-space. 335 * 336 * u32 seq, time_mult, time_shift, idx, width; 337 * u64 count, enabled, running; 338 * u64 cyc, time_offset; 339 * s64 pmc = 0; 340 * 341 * do { 342 * seq = pc->lock; 343 * barrier() 344 * 345 * enabled = pc->time_enabled; 346 * running = pc->time_running; 347 * 348 * if (pc->cap_usr_time && enabled != running) { 349 * cyc = rdtsc(); 350 * time_offset = pc->time_offset; 351 * time_mult = pc->time_mult; 352 * time_shift = pc->time_shift; 353 * } 354 * 355 * idx = pc->index; 356 * count = pc->offset; 357 * if (pc->cap_usr_rdpmc && idx) { 358 * width = pc->pmc_width; 359 * pmc = rdpmc(idx - 1); 360 * } 361 * 362 * barrier(); 363 * } while (pc->lock != seq); 364 * 365 * NOTE: for obvious reason this only works on self-monitoring 366 * processes. 367 */ 368 __u32 lock; /* seqlock for synchronization */ 369 __u32 index; /* hardware event identifier */ 370 __s64 offset; /* add to hardware event value */ 371 __u64 time_enabled; /* time event active */ 372 __u64 time_running; /* time event on cpu */ 373 union { 374 __u64 capabilities; 375 __u64 cap_usr_time : 1, 376 cap_usr_rdpmc : 1, 377 cap_____res : 62; 378 }; 379 380 /* 381 * If cap_usr_rdpmc this field provides the bit-width of the value 382 * read using the rdpmc() or equivalent instruction. This can be used 383 * to sign extend the result like: 384 * 385 * pmc <<= 64 - width; 386 * pmc >>= 64 - width; // signed shift right 387 * count += pmc; 388 */ 389 __u16 pmc_width; 390 391 /* 392 * If cap_usr_time the below fields can be used to compute the time 393 * delta since time_enabled (in ns) using rdtsc or similar. 394 * 395 * u64 quot, rem; 396 * u64 delta; 397 * 398 * quot = (cyc >> time_shift); 399 * rem = cyc & ((1 << time_shift) - 1); 400 * delta = time_offset + quot * time_mult + 401 * ((rem * time_mult) >> time_shift); 402 * 403 * Where time_offset,time_mult,time_shift and cyc are read in the 404 * seqcount loop described above. This delta can then be added to 405 * enabled and possible running (if idx), improving the scaling: 406 * 407 * enabled += delta; 408 * if (idx) 409 * running += delta; 410 * 411 * quot = count / running; 412 * rem = count % running; 413 * count = quot * enabled + (rem * enabled) / running; 414 */ 415 __u16 time_shift; 416 __u32 time_mult; 417 __u64 time_offset; 418 419 /* 420 * Hole for extension of the self monitor capabilities 421 */ 422 423 __u64 __reserved[120]; /* align to 1k */ 424 425 /* 426 * Control data for the mmap() data buffer. 427 * 428 * User-space reading the @data_head value should issue an rmb(), on 429 * SMP capable platforms, after reading this value -- see 430 * perf_event_wakeup(). 431 * 432 * When the mapping is PROT_WRITE the @data_tail value should be 433 * written by userspace to reflect the last read data. In this case 434 * the kernel will not over-write unread data. 435 */ 436 __u64 data_head; /* head in the data section */ 437 __u64 data_tail; /* user-space written tail */ 438 }; 439 440 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 441 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 442 #define PERF_RECORD_MISC_KERNEL (1 << 0) 443 #define PERF_RECORD_MISC_USER (2 << 0) 444 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 445 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 446 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 447 448 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 449 /* 450 * Indicates that the content of PERF_SAMPLE_IP points to 451 * the actual instruction that triggered the event. See also 452 * perf_event_attr::precise_ip. 453 */ 454 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 455 /* 456 * Reserve the last bit to indicate some extended misc field 457 */ 458 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 459 460 struct perf_event_header { 461 __u32 type; 462 __u16 misc; 463 __u16 size; 464 }; 465 466 enum perf_event_type { 467 468 /* 469 * If perf_event_attr.sample_id_all is set then all event types will 470 * have the sample_type selected fields related to where/when 471 * (identity) an event took place (TID, TIME, ID, CPU, STREAM_ID) 472 * described in PERF_RECORD_SAMPLE below, it will be stashed just after 473 * the perf_event_header and the fields already present for the existing 474 * fields, i.e. at the end of the payload. That way a newer perf.data 475 * file will be supported by older perf tools, with these new optional 476 * fields being ignored. 477 * 478 * The MMAP events record the PROT_EXEC mappings so that we can 479 * correlate userspace IPs to code. They have the following structure: 480 * 481 * struct { 482 * struct perf_event_header header; 483 * 484 * u32 pid, tid; 485 * u64 addr; 486 * u64 len; 487 * u64 pgoff; 488 * char filename[]; 489 * }; 490 */ 491 PERF_RECORD_MMAP = 1, 492 493 /* 494 * struct { 495 * struct perf_event_header header; 496 * u64 id; 497 * u64 lost; 498 * }; 499 */ 500 PERF_RECORD_LOST = 2, 501 502 /* 503 * struct { 504 * struct perf_event_header header; 505 * 506 * u32 pid, tid; 507 * char comm[]; 508 * }; 509 */ 510 PERF_RECORD_COMM = 3, 511 512 /* 513 * struct { 514 * struct perf_event_header header; 515 * u32 pid, ppid; 516 * u32 tid, ptid; 517 * u64 time; 518 * }; 519 */ 520 PERF_RECORD_EXIT = 4, 521 522 /* 523 * struct { 524 * struct perf_event_header header; 525 * u64 time; 526 * u64 id; 527 * u64 stream_id; 528 * }; 529 */ 530 PERF_RECORD_THROTTLE = 5, 531 PERF_RECORD_UNTHROTTLE = 6, 532 533 /* 534 * struct { 535 * struct perf_event_header header; 536 * u32 pid, ppid; 537 * u32 tid, ptid; 538 * u64 time; 539 * }; 540 */ 541 PERF_RECORD_FORK = 7, 542 543 /* 544 * struct { 545 * struct perf_event_header header; 546 * u32 pid, tid; 547 * 548 * struct read_format values; 549 * }; 550 */ 551 PERF_RECORD_READ = 8, 552 553 /* 554 * struct { 555 * struct perf_event_header header; 556 * 557 * { u64 ip; } && PERF_SAMPLE_IP 558 * { u32 pid, tid; } && PERF_SAMPLE_TID 559 * { u64 time; } && PERF_SAMPLE_TIME 560 * { u64 addr; } && PERF_SAMPLE_ADDR 561 * { u64 id; } && PERF_SAMPLE_ID 562 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 563 * { u32 cpu, res; } && PERF_SAMPLE_CPU 564 * { u64 period; } && PERF_SAMPLE_PERIOD 565 * 566 * { struct read_format values; } && PERF_SAMPLE_READ 567 * 568 * { u64 nr, 569 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 570 * 571 * # 572 * # The RAW record below is opaque data wrt the ABI 573 * # 574 * # That is, the ABI doesn't make any promises wrt to 575 * # the stability of its content, it may vary depending 576 * # on event, hardware, kernel version and phase of 577 * # the moon. 578 * # 579 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 580 * # 581 * 582 * { u32 size; 583 * char data[size];}&& PERF_SAMPLE_RAW 584 * 585 * { u64 nr; 586 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK 587 * 588 * { u64 abi; # enum perf_sample_regs_abi 589 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 590 * 591 * { u64 size; 592 * char data[size]; 593 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 594 * 595 * { u64 weight; } && PERF_SAMPLE_WEIGHT 596 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 597 * }; 598 */ 599 PERF_RECORD_SAMPLE = 9, 600 601 PERF_RECORD_MAX, /* non-ABI */ 602 }; 603 604 #define PERF_MAX_STACK_DEPTH 127 605 606 enum perf_callchain_context { 607 PERF_CONTEXT_HV = (__u64)-32, 608 PERF_CONTEXT_KERNEL = (__u64)-128, 609 PERF_CONTEXT_USER = (__u64)-512, 610 611 PERF_CONTEXT_GUEST = (__u64)-2048, 612 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 613 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 614 615 PERF_CONTEXT_MAX = (__u64)-4095, 616 }; 617 618 #define PERF_FLAG_FD_NO_GROUP (1U << 0) 619 #define PERF_FLAG_FD_OUTPUT (1U << 1) 620 #define PERF_FLAG_PID_CGROUP (1U << 2) /* pid=cgroup id, per-cpu mode only */ 621 622 union perf_mem_data_src { 623 __u64 val; 624 struct { 625 __u64 mem_op:5, /* type of opcode */ 626 mem_lvl:14, /* memory hierarchy level */ 627 mem_snoop:5, /* snoop mode */ 628 mem_lock:2, /* lock instr */ 629 mem_dtlb:7, /* tlb access */ 630 mem_rsvd:31; 631 }; 632 }; 633 634 /* type of opcode (load/store/prefetch,code) */ 635 #define PERF_MEM_OP_NA 0x01 /* not available */ 636 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 637 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 638 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 639 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 640 #define PERF_MEM_OP_SHIFT 0 641 642 /* memory hierarchy (memory level, hit or miss) */ 643 #define PERF_MEM_LVL_NA 0x01 /* not available */ 644 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 645 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 646 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 647 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 648 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 649 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 650 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 651 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 652 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 653 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 654 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 655 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 656 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 657 #define PERF_MEM_LVL_SHIFT 5 658 659 /* snoop mode */ 660 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 661 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 662 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 663 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 664 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 665 #define PERF_MEM_SNOOP_SHIFT 19 666 667 /* locked instruction */ 668 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 669 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 670 #define PERF_MEM_LOCK_SHIFT 24 671 672 /* TLB access */ 673 #define PERF_MEM_TLB_NA 0x01 /* not available */ 674 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 675 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 676 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 677 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 678 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 679 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 680 #define PERF_MEM_TLB_SHIFT 26 681 682 #define PERF_MEM_S(a, s) \ 683 (((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 684 685 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 686