1 /* 2 * Si5351A/B/C programmable clock generator platform_data. 3 */ 4 5 #ifndef __LINUX_PLATFORM_DATA_SI5351_H__ 6 #define __LINUX_PLATFORM_DATA_SI5351_H__ 7 8 struct clk; 9 10 /** 11 * enum si5351_variant - SiLabs Si5351 chip variant 12 * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input) 13 * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input) 14 * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input) 15 * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input) 16 */ 17 enum si5351_variant { 18 SI5351_VARIANT_A = 1, 19 SI5351_VARIANT_A3 = 2, 20 SI5351_VARIANT_B = 3, 21 SI5351_VARIANT_C = 4, 22 }; 23 24 /** 25 * enum si5351_pll_src - Si5351 pll clock source 26 * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config 27 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input 28 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only) 29 */ 30 enum si5351_pll_src { 31 SI5351_PLL_SRC_DEFAULT = 0, 32 SI5351_PLL_SRC_XTAL = 1, 33 SI5351_PLL_SRC_CLKIN = 2, 34 }; 35 36 /** 37 * enum si5351_multisynth_src - Si5351 multisynth clock source 38 * @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config 39 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0 40 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO 41 */ 42 enum si5351_multisynth_src { 43 SI5351_MULTISYNTH_SRC_DEFAULT = 0, 44 SI5351_MULTISYNTH_SRC_VCO0 = 1, 45 SI5351_MULTISYNTH_SRC_VCO1 = 2, 46 }; 47 48 /** 49 * enum si5351_clkout_src - Si5351 clock output clock source 50 * @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config 51 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N 52 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4) 53 * or 4 (N>=4) 54 * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL 55 * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only) 56 */ 57 enum si5351_clkout_src { 58 SI5351_CLKOUT_SRC_DEFAULT = 0, 59 SI5351_CLKOUT_SRC_MSYNTH_N = 1, 60 SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2, 61 SI5351_CLKOUT_SRC_XTAL = 3, 62 SI5351_CLKOUT_SRC_CLKIN = 4, 63 }; 64 65 /** 66 * enum si5351_drive_strength - Si5351 clock output drive strength 67 * @SI5351_DRIVE_DEFAULT: default, do not change eeprom config 68 * @SI5351_DRIVE_2MA: 2mA clock output drive strength 69 * @SI5351_DRIVE_4MA: 4mA clock output drive strength 70 * @SI5351_DRIVE_6MA: 6mA clock output drive strength 71 * @SI5351_DRIVE_8MA: 8mA clock output drive strength 72 */ 73 enum si5351_drive_strength { 74 SI5351_DRIVE_DEFAULT = 0, 75 SI5351_DRIVE_2MA = 2, 76 SI5351_DRIVE_4MA = 4, 77 SI5351_DRIVE_6MA = 6, 78 SI5351_DRIVE_8MA = 8, 79 }; 80 81 /** 82 * struct si5351_clkout_config - Si5351 clock output configuration 83 * @clkout: clkout number 84 * @multisynth_src: multisynth source clock 85 * @clkout_src: clkout source clock 86 * @pll_master: if true, clkout can also change pll rate 87 * @drive: output drive strength 88 * @rate: initial clkout rate, or default if 0 89 */ 90 struct si5351_clkout_config { 91 enum si5351_multisynth_src multisynth_src; 92 enum si5351_clkout_src clkout_src; 93 enum si5351_drive_strength drive; 94 bool pll_master; 95 unsigned long rate; 96 }; 97 98 /** 99 * struct si5351_platform_data - Platform data for the Si5351 clock driver 100 * @variant: Si5351 chip variant 101 * @clk_xtal: xtal input clock 102 * @clk_clkin: clkin input clock 103 * @pll_src: array of pll source clock setting 104 * @clkout: array of clkout configuration 105 */ 106 struct si5351_platform_data { 107 enum si5351_variant variant; 108 struct clk *clk_xtal; 109 struct clk *clk_clkin; 110 enum si5351_pll_src pll_src[2]; 111 struct si5351_clkout_config clkout[8]; 112 }; 113 114 #endif 115