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Searched refs:TRUE (Results 1 – 20 of 20) sorted by relevance

/sound/oss/
Daedsp16.c270 #define TRUE 1 macro
516 return TRUE; in aedsp16_wait_data()
543 return ((aedsp16_read(port) == 0xaa) ? TRUE : FALSE); in aedsp16_test_dsp()
559 if (aedsp16_test_dsp(port) == TRUE) { in aedsp16_dsp_reset()
561 return TRUE; in aedsp16_dsp_reset()
706 return TRUE; in aedsp16_hard_write()
740 return TRUE; in aedsp16_hard_read()
792 return TRUE; in aedsp16_ext_cfg_write()
806 return TRUE; in aedsp16_cfg_write()
831 return TRUE; in aedsp16_init_mss()
[all …]
Dos.h28 #define TRUE 1 macro
/sound/pci/echoaudio/
Dlayla24_dsp.c54 chip->bad_board = TRUE; in init_hw()
55 chip->has_midi = TRUE; in init_hw()
82 chip->digital_in_automute = TRUE; in set_mixer_defaults()
152 TRUE); in load_asic()
295 return write_control_reg(chip, control_reg, TRUE); in set_input_clock()
347 incompatible_clock = TRUE; in dsp_set_digital_mode()
352 incompatible_clock = TRUE; in dsp_set_digital_mode()
390 err = write_control_reg(chip, control_reg, TRUE); in dsp_set_digital_mode()
Dgina24_dsp.c55 chip->bad_board = TRUE; in init_hw()
91 chip->digital_in_automute = TRUE; in set_mixer_defaults()
156 err = write_control_reg(chip, control_reg, TRUE); in load_asic()
283 return write_control_reg(chip, control_reg, TRUE); in set_input_clock()
300 incompatible_clock = TRUE; in dsp_set_digital_mode()
304 incompatible_clock = TRUE; in dsp_set_digital_mode()
341 err = write_control_reg(chip, control_reg, TRUE); in dsp_set_digital_mode()
Decho3g_dsp.c62 chip->bad_board = TRUE; in init_hw()
63 chip->has_midi = TRUE; in init_hw()
81 chip->has_phantom_power = TRUE; in init_hw()
82 chip->hasnt_input_nominal_level = TRUE; in init_hw()
Dmona_dsp.c55 chip->bad_board = TRUE; in init_hw()
84 chip->digital_in_automute = TRUE; in set_mixer_defaults()
152 err = write_control_reg(chip, control_reg, TRUE); in load_asic()
361 return write_control_reg(chip, control_reg, TRUE); in set_input_clock()
377 incompatible_clock = TRUE; in dsp_set_digital_mode()
381 incompatible_clock = TRUE; in dsp_set_digital_mode()
Dindigodjx_dsp.c50 chip->bad_board = TRUE; in init_hw()
54 chip->asic_loaded = TRUE; in init_hw()
Dindigoiox_dsp.c50 chip->bad_board = TRUE; in init_hw()
54 chip->asic_loaded = TRUE; in init_hw()
Dmia_dsp.c55 chip->bad_board = TRUE; in init_hw()
59 chip->asic_loaded = TRUE; in init_hw()
61 chip->has_midi = TRUE; in init_hw()
Dlayla20_dsp.c54 chip->bad_board = TRUE; in init_hw()
55 chip->has_midi = TRUE; in init_hw()
130 chip->asic_loaded = TRUE; in check_asic_status()
Ddarla20_dsp.c47 chip->bad_board = TRUE; in init_hw()
53 chip->asic_loaded = TRUE; in init_hw()
Dindigoio_dsp.c52 chip->bad_board = TRUE; in init_hw()
56 chip->asic_loaded = TRUE; in init_hw()
Ddarla24_dsp.c47 chip->bad_board = TRUE; in init_hw()
51 chip->asic_loaded = TRUE; in init_hw()
Dechoaudio_3g.c58 chip->asic_loaded = TRUE; in check_asic_status()
245 E3G_FREQ_REG_DEFAULT, TRUE); in load_asic()
388 incompatible_clock = TRUE; in dsp_set_digital_mode()
392 incompatible_clock = TRUE; in dsp_set_digital_mode()
Dindigo_dsp.c52 chip->bad_board = TRUE; in init_hw()
56 chip->asic_loaded = TRUE; in init_hw()
Dindigodj_dsp.c52 chip->bad_board = TRUE; in init_hw()
56 chip->asic_loaded = TRUE; in init_hw()
Dgina20_dsp.c51 chip->bad_board = TRUE; in init_hw()
57 chip->asic_loaded = TRUE; in init_hw()
Dechoaudio_dsp.c106 chip->bad_board = TRUE; /* Set TRUE until DSP re-loaded */ in write_dsp()
129 chip->bad_board = TRUE; /* Set TRUE until DSP re-loaded */ in read_dsp()
167 chip->asic_loaded = TRUE; in check_asic_status()
339 chip->bad_board = TRUE; /* Set TRUE until DSP loaded */ in load_dsp()
973 chip->bad_board = TRUE; /* Set TRUE until DSP loaded */ in init_dsp_comm_page()
Dechoaudio.h156 #define TRUE 1 macro
Dechoaudio.c2303 enable_midi_input(chip, TRUE); in snd_echo_resume()