Searched refs:TZIC_ENSET0 (Results 1 – 1 of 1) sorted by relevance
41 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ macro91 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), in tzic_irq_resume()123 ct->regs.enable = TZIC_ENSET0(idx); in tzic_init_gc()218 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), in tzic_enable_wake()