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Searched refs:XCHAL_HAVE_TLBS (Results 1 – 5 of 5) sorted by relevance

/arch/xtensa/include/asm/
Dmmu_context.h30 #if (XCHAL_HAVE_TLBS != 1)
/arch/xtensa/variants/fsf/include/variant/
Dcore.h338 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/dc232b/include/variant/
Dcore.h403 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/s6000/include/variant/
Dcore.h412 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro
/arch/xtensa/variants/dc233c/include/variant/
Dcore.h453 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ macro