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Searched refs:ctlr (Results 1 – 6 of 6) sorted by relevance

/arch/arm/mach-davinci/
Ddma.c107 static inline unsigned int edma_read(unsigned ctlr, int offset) in edma_read() argument
109 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); in edma_read()
112 static inline void edma_write(unsigned ctlr, int offset, int val) in edma_write() argument
114 __raw_writel(val, edmacc_regs_base[ctlr] + offset); in edma_write()
116 static inline void edma_modify(unsigned ctlr, int offset, unsigned and, in edma_modify() argument
119 unsigned val = edma_read(ctlr, offset); in edma_modify()
122 edma_write(ctlr, offset, val); in edma_modify()
124 static inline void edma_and(unsigned ctlr, int offset, unsigned and) in edma_and() argument
126 unsigned val = edma_read(ctlr, offset); in edma_and()
128 edma_write(ctlr, offset, val); in edma_and()
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Dpsc.c31 int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) in davinci_psc_is_clk_active() argument
37 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { in davinci_psc_is_clk_active()
39 (int)soc_info->psc_bases, ctlr); in davinci_psc_is_clk_active()
43 psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); in davinci_psc_is_clk_active()
52 void davinci_psc_reset(unsigned int ctlr, unsigned int id, bool reset) in davinci_psc_reset() argument
58 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { in davinci_psc_reset()
60 (int)soc_info->psc_bases, ctlr); in davinci_psc_reset()
64 psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); in davinci_psc_reset()
77 void davinci_psc_config(unsigned int domain, unsigned int ctlr, in davinci_psc_config() argument
85 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { in davinci_psc_config()
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/arch/arm/mach-davinci/include/mach/
Dgpio.h36 struct davinci_gpio_controller *ctlr; in gpio_set_value() local
39 ctlr = __gpio_to_controller(gpio); in gpio_set_value()
41 if (ctlr->set_data != ctlr->clr_data) { in gpio_set_value()
44 __raw_writel(mask, ctlr->set_data); in gpio_set_value()
46 __raw_writel(mask, ctlr->clr_data); in gpio_set_value()
65 struct davinci_gpio_controller *ctlr; in gpio_get_value() local
70 ctlr = __gpio_to_controller(gpio); in gpio_get_value()
71 return __gpio_mask(gpio) & __raw_readl(ctlr->in_data); in gpio_get_value()
Dedma.h187 #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) argument
206 int edma_alloc_slot(unsigned ctlr, int slot);
210 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
Dpsc.h256 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
257 extern void davinci_psc_reset(unsigned int ctlr, unsigned int id,
259 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
/arch/powerpc/include/asm/
Dmpc52xx_psc.h188 u8 ctlr; /* PSC + 0x1c */ member