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Searched refs:upa_writeq (Results 1 – 9 of 9) sorted by relevance

/arch/sparc/kernel/
Dpci_fire.c55 upa_writeq(~(u64)0, iommu->iommu_flushinv); in pci_fire_pbm_iommu_init()
62 upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase); in pci_fire_pbm_iommu_init()
69 upa_writeq(control, iommu->iommu_control); in pci_fire_pbm_iommu_init()
177 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num)); in pci_fire_dequeue_msi()
193 upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid)); in pci_fire_set_head()
205 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
207 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi)); in pci_fire_msi_setup()
211 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
224 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_teardown()
243 upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES | in pci_fire_msiq_alloc()
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Dpsycho_common.c58 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
63 upa_writeq(0UL, err_base + (i * 8UL)); in psycho_check_stc_error()
69 upa_writeq(0UL, tag_base + (i * 8UL)); in psycho_check_stc_error()
70 upa_writeq(0UL, line_base + (i * 8UL)); in psycho_check_stc_error()
74 upa_writeq(control, strbuf->strbuf_control); in psycho_check_stc_error()
137 upa_writeq(0, base + PSYCHO_IOMMU_TAG + off); in psycho_record_iommu_tags_and_data()
138 upa_writeq(0, base + PSYCHO_IOMMU_DATA + off); in psycho_record_iommu_tags_and_data()
215 upa_writeq(control, iommu->iommu_control); in psycho_check_iommu_error()
261 upa_writeq(csr, pbm->pci_csr); in psycho_pcierr_intr_other()
318 upa_writeq(error_bits, pbm->pci_afsr); in psycho_pcierr_intr()
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Dpci_schizo.c151 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB), in __schizo_check_stc_error_pbm()
157 upa_writeq(0UL, err_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
163 upa_writeq(0UL, tag_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
164 upa_writeq(0UL, line_base + (i * 8UL)); in __schizo_check_stc_error_pbm()
168 upa_writeq(control, strbuf->strbuf_control); in __schizo_check_stc_error_pbm()
252 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
282 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB, in schizo_check_iommu_error_pbm()
294 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL)); in schizo_check_iommu_error_pbm()
295 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL)); in schizo_check_iommu_error_pbm()
299 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
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Dsbus.c119 upa_writeq(val, cfg_reg); in sbus_set_sbus64()
289 upa_writeq(error_bits, afsr_reg); in sysio_ue_handler()
363 upa_writeq(error_bits, afsr_reg); in sysio_ce_handler()
441 upa_writeq(error_bits, afsr_reg); in sysio_sbus_error_handler()
527 upa_writeq((SYSIO_ECNTRL_ECCEN | in sysio_register_error_handlers()
534 upa_writeq(control, iommu->write_complete_reg); in sysio_register_error_handlers()
604 upa_writeq(control, iommu->iommu_control); in sbus_iommu_init()
617 upa_writeq(0, dram); in sbus_iommu_init()
618 upa_writeq(0, tag); in sbus_iommu_init()
623 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase); in sbus_iommu_init()
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Dpci_psycho.c150 upa_writeq(error_bits, afsr_reg); in psycho_ue_intr()
229 upa_writeq(error_bits, afsr_reg); in psycho_ce_intr()
329 upa_writeq((PSYCHO_ECCCTRL_EE | in psycho_register_error_handlers()
341 upa_writeq(tmp, base + PSYCHO_PCIA_CTRL); in psycho_register_error_handlers()
348 upa_writeq(tmp, base + PSYCHO_PCIB_CTRL); in psycho_register_error_handlers()
398 upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY); in psycho_controller_hwinit()
403 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL); in psycho_controller_hwinit()
407 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL); in psycho_controller_hwinit()
415 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG); in psycho_controller_hwinit()
419 upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG); in psycho_controller_hwinit()
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Dpci_sabre.c215 upa_writeq(error_bits, afsr_reg); in sabre_ue_intr()
274 upa_writeq(error_bits, afsr_reg); in sabre_ce_intr()
340 upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR | in sabre_register_error_handlers()
350 upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR | in sabre_register_error_handlers()
367 upa_writeq(tmp, base + SABRE_PCICTRL); in sabre_register_error_handlers()
521 upa_writeq(0x0UL, pbm->controller_regs + clear_irq); in sabre_probe()
525 upa_writeq(0x0UL, pbm->controller_regs + clear_irq); in sabre_probe()
528 upa_writeq((SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR | in sabre_probe()
Dirq_64.c258 upa_writeq(val, imap); in sun4u_irq_enable()
259 upa_writeq(ICLR_IDLE, handler_data->iclr); in sun4u_irq_enable()
281 upa_writeq(val, imap); in sun4u_set_affinity()
282 upa_writeq(ICLR_IDLE, handler_data->iclr); in sun4u_set_affinity()
314 upa_writeq(ICLR_IDLE, handler_data->iclr); in sun4u_irq_eoi()
Dprom_irqtrans.c526 upa_writeq(int_ctrlr, imap); in fire_irq_build()
/arch/sparc/include/asm/
Dupa.h106 #define upa_writeq(__q, __addr) (_upa_writeq((__q), (unsigned long)(__addr))) macro