1 /* 2 * linux/arch/arm/include/asm/hardware/coresight.h 3 * 4 * CoreSight components' registers 5 * 6 * Copyright (C) 2009 Nokia Corporation. 7 * Alexander Shishkin 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #ifndef __ASM_HARDWARE_CORESIGHT_H 15 #define __ASM_HARDWARE_CORESIGHT_H 16 17 #define TRACER_ACCESSED_BIT 0 18 #define TRACER_RUNNING_BIT 1 19 #define TRACER_CYCLE_ACC_BIT 2 20 #define TRACER_TRACE_DATA_BIT 3 21 #define TRACER_TIMESTAMP_BIT 4 22 #define TRACER_BRANCHOUTPUT_BIT 5 23 #define TRACER_RETURN_STACK_BIT 6 24 #define TRACER_ACCESSED BIT(TRACER_ACCESSED_BIT) 25 #define TRACER_RUNNING BIT(TRACER_RUNNING_BIT) 26 #define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT) 27 #define TRACER_TRACE_DATA BIT(TRACER_TRACE_DATA_BIT) 28 #define TRACER_TIMESTAMP BIT(TRACER_TIMESTAMP_BIT) 29 #define TRACER_BRANCHOUTPUT BIT(TRACER_BRANCHOUTPUT_BIT) 30 #define TRACER_RETURN_STACK BIT(TRACER_RETURN_STACK_BIT) 31 32 #define TRACER_TIMEOUT 10000 33 34 #define etm_writel(t, id, v, x) \ 35 (__raw_writel((v), (t)->etm_regs[(id)] + (x))) 36 #define etm_readl(t, id, x) (__raw_readl((t)->etm_regs[(id)] + (x))) 37 38 /* CoreSight Management Registers */ 39 #define CSMR_LOCKACCESS 0xfb0 40 #define CSMR_LOCKSTATUS 0xfb4 41 #define CSMR_AUTHSTATUS 0xfb8 42 #define CSMR_DEVID 0xfc8 43 #define CSMR_DEVTYPE 0xfcc 44 /* CoreSight Component Registers */ 45 #define CSCR_CLASS 0xff4 46 47 #define CS_LAR_KEY 0xc5acce55 48 49 /* ETM control register, "ETM Architecture", 3.3.1 */ 50 #define ETMR_CTRL 0 51 #define ETMCTRL_POWERDOWN 1 52 #define ETMCTRL_PROGRAM (1 << 10) 53 #define ETMCTRL_PORTSEL (1 << 11) 54 #define ETMCTRL_CONTEXTIDSIZE(x) (((x) & 3) << 14) 55 #define ETMCTRL_PORTMASK1 (7 << 4) 56 #define ETMCTRL_PORTMASK2 (1 << 21) 57 #define ETMCTRL_PORTMASK (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2) 58 #define ETMCTRL_PORTSIZE(x) ((((x) & 7) << 4) | (!!((x) & 8)) << 21) 59 #define ETMCTRL_DO_CPRT (1 << 1) 60 #define ETMCTRL_DATAMASK (3 << 2) 61 #define ETMCTRL_DATA_DO_DATA (1 << 2) 62 #define ETMCTRL_DATA_DO_ADDR (1 << 3) 63 #define ETMCTRL_DATA_DO_BOTH (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR) 64 #define ETMCTRL_BRANCH_OUTPUT (1 << 8) 65 #define ETMCTRL_CYCLEACCURATE (1 << 12) 66 #define ETMCTRL_TIMESTAMP_EN (1 << 28) 67 #define ETMCTRL_RETURN_STACK_EN (1 << 29) 68 69 /* ETM configuration code register */ 70 #define ETMR_CONFCODE (0x04) 71 #define ETMCCR_ETMIDR_PRESENT BIT(31) 72 73 /* ETM trace start/stop resource control register */ 74 #define ETMR_TRACESSCTRL (0x18) 75 76 /* ETM trigger event register */ 77 #define ETMR_TRIGEVT (0x08) 78 79 /* address access type register bits, "ETM architecture", 80 * table 3-27 */ 81 /* - access type */ 82 #define ETMAAT_IFETCH 0 83 #define ETMAAT_IEXEC 1 84 #define ETMAAT_IEXECPASS 2 85 #define ETMAAT_IEXECFAIL 3 86 #define ETMAAT_DLOADSTORE 4 87 #define ETMAAT_DLOAD 5 88 #define ETMAAT_DSTORE 6 89 /* - comparison access size */ 90 #define ETMAAT_JAVA (0 << 3) 91 #define ETMAAT_THUMB (1 << 3) 92 #define ETMAAT_ARM (3 << 3) 93 /* - data value comparison control */ 94 #define ETMAAT_NOVALCMP (0 << 5) 95 #define ETMAAT_VALMATCH (1 << 5) 96 #define ETMAAT_VALNOMATCH (3 << 5) 97 /* - exact match */ 98 #define ETMAAT_EXACTMATCH (1 << 7) 99 /* - context id comparator control */ 100 #define ETMAAT_IGNCONTEXTID (0 << 8) 101 #define ETMAAT_VALUE1 (1 << 8) 102 #define ETMAAT_VALUE2 (2 << 8) 103 #define ETMAAT_VALUE3 (3 << 8) 104 /* - security level control */ 105 #define ETMAAT_IGNSECURITY (0 << 10) 106 #define ETMAAT_NSONLY (1 << 10) 107 #define ETMAAT_SONLY (2 << 10) 108 109 #define ETMR_COMP_VAL(x) (0x40 + (x) * 4) 110 #define ETMR_COMP_ACC_TYPE(x) (0x80 + (x) * 4) 111 112 /* ETM status register, "ETM Architecture", 3.3.2 */ 113 #define ETMR_STATUS (0x10) 114 #define ETMST_OVERFLOW BIT(0) 115 #define ETMST_PROGBIT BIT(1) 116 #define ETMST_STARTSTOP BIT(2) 117 #define ETMST_TRIGGER BIT(3) 118 119 #define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT) 120 #define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP) 121 #define etm_triggered(t) (etm_readl((t), ETMR_STATUS) & ETMST_TRIGGER) 122 123 #define ETMR_TRACEENCTRL2 0x1c 124 #define ETMR_TRACEENCTRL 0x24 125 #define ETMTE_INCLEXCL BIT(24) 126 #define ETMR_TRACEENEVT 0x20 127 128 #define ETMR_VIEWDATAEVT 0x30 129 #define ETMR_VIEWDATACTRL1 0x34 130 #define ETMR_VIEWDATACTRL2 0x38 131 #define ETMR_VIEWDATACTRL3 0x3c 132 #define ETMVDC3_EXCLONLY BIT(16) 133 134 #define ETMCTRL_OPTS (ETMCTRL_DO_CPRT) 135 136 #define ETMR_ID 0x1e4 137 #define ETMIDR_VERSION(x) (((x) >> 4) & 0xff) 138 #define ETMIDR_VERSION_3_1 0x21 139 #define ETMIDR_VERSION_PFT_1_0 0x30 140 141 #define ETMR_CCE 0x1e8 142 #define ETMCCER_RETURN_STACK_IMPLEMENTED BIT(23) 143 #define ETMCCER_TIMESTAMPING_IMPLEMENTED BIT(22) 144 145 #define ETMR_TRACEIDR 0x200 146 147 /* ETM management registers, "ETM Architecture", 3.5.24 */ 148 #define ETMMR_OSLAR 0x300 149 #define ETMMR_OSLSR 0x304 150 #define ETMMR_OSSRR 0x308 151 #define ETMMR_PDSR 0x314 152 153 /* ETB registers, "CoreSight Components TRM", 9.3 */ 154 #define ETBR_DEPTH 0x04 155 #define ETBR_STATUS 0x0c 156 #define ETBR_READMEM 0x10 157 #define ETBR_READADDR 0x14 158 #define ETBR_WRITEADDR 0x18 159 #define ETBR_TRIGGERCOUNT 0x1c 160 #define ETBR_CTRL 0x20 161 #define ETBR_FORMATTERCTRL 0x304 162 #define ETBFF_ENFTC 1 163 #define ETBFF_ENFCONT BIT(1) 164 #define ETBFF_FONFLIN BIT(4) 165 #define ETBFF_MANUAL_FLUSH BIT(6) 166 #define ETBFF_TRIGIN BIT(8) 167 #define ETBFF_TRIGEVT BIT(9) 168 #define ETBFF_TRIGFL BIT(10) 169 #define ETBFF_STOPFL BIT(12) 170 171 #define etb_writel(t, v, x) \ 172 (__raw_writel((v), (t)->etb_regs + (x))) 173 #define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x))) 174 175 #define etm_lock(t, id) \ 176 do { etm_writel((t), (id), 0, CSMR_LOCKACCESS); } while (0) 177 #define etm_unlock(t, id) \ 178 do { etm_writel((t), (id), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0) 179 180 #define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0) 181 #define etb_unlock(t) \ 182 do { etb_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0) 183 184 #endif /* __ASM_HARDWARE_CORESIGHT_H */ 185 186