1 /* 2 * arch/arm/mach-at91/include/mach/at91_pio.h 3 * 4 * Copyright (C) 2005 Ivan Kokshaysky 5 * Copyright (C) SAN People 6 * 7 * Parallel I/O Controller (PIO) - System peripherals registers. 8 * Based on AT91RM9200 datasheet revision E. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #ifndef AT91_PIO_H 17 #define AT91_PIO_H 18 19 #define PIO_PER 0x00 /* Enable Register */ 20 #define PIO_PDR 0x04 /* Disable Register */ 21 #define PIO_PSR 0x08 /* Status Register */ 22 #define PIO_OER 0x10 /* Output Enable Register */ 23 #define PIO_ODR 0x14 /* Output Disable Register */ 24 #define PIO_OSR 0x18 /* Output Status Register */ 25 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ 26 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ 27 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ 28 #define PIO_SODR 0x30 /* Set Output Data Register */ 29 #define PIO_CODR 0x34 /* Clear Output Data Register */ 30 #define PIO_ODSR 0x38 /* Output Data Status Register */ 31 #define PIO_PDSR 0x3c /* Pin Data Status Register */ 32 #define PIO_IER 0x40 /* Interrupt Enable Register */ 33 #define PIO_IDR 0x44 /* Interrupt Disable Register */ 34 #define PIO_IMR 0x48 /* Interrupt Mask Register */ 35 #define PIO_ISR 0x4c /* Interrupt Status Register */ 36 #define PIO_MDER 0x50 /* Multi-driver Enable Register */ 37 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ 38 #define PIO_MDSR 0x58 /* Multi-driver Status Register */ 39 #define PIO_PUDR 0x60 /* Pull-up Disable Register */ 40 #define PIO_PUER 0x64 /* Pull-up Enable Register */ 41 #define PIO_PUSR 0x68 /* Pull-up Status Register */ 42 #define PIO_ASR 0x70 /* Peripheral A Select Register */ 43 #define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */ 44 #define PIO_BSR 0x74 /* Peripheral B Select Register */ 45 #define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */ 46 #define PIO_ABSR 0x78 /* AB Status Register */ 47 #define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */ 48 #define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */ 49 #define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */ 50 #define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */ 51 #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ 52 #define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */ 53 #define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */ 54 #define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */ 55 #define PIO_OWER 0xa0 /* Output Write Enable Register */ 56 #define PIO_OWDR 0xa4 /* Output Write Disable Register */ 57 #define PIO_OWSR 0xa8 /* Output Write Status Register */ 58 #define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */ 59 #define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */ 60 #define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */ 61 #define PIO_ESR 0xc0 /* Edge Select Register */ 62 #define PIO_LSR 0xc4 /* Level Select Register */ 63 #define PIO_ELSR 0xc8 /* Edge/Level Status Register */ 64 #define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */ 65 #define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */ 66 #define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */ 67 #define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */ 68 69 #define ABCDSR_PERIPH_A 0x0 70 #define ABCDSR_PERIPH_B 0x1 71 #define ABCDSR_PERIPH_C 0x2 72 #define ABCDSR_PERIPH_D 0x3 73 74 #endif 75