1 #include <linux/clk.h>
2 #include <linux/io.h>
3 #include <linux/module.h>
4 #include <linux/clkdev.h>
5 #include <linux/err.h>
6 #include <linux/clk-provider.h>
7 #include <linux/of.h>
8
9 #include "clk.h"
10 #include "common.h"
11 #include "hardware.h"
12
13 #define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
14
15 /* Register offsets */
16 #define CCM_CSCR IO_ADDR_CCM(0x0)
17 #define CCM_MPCTL0 IO_ADDR_CCM(0x4)
18 #define CCM_MPCTL1 IO_ADDR_CCM(0x8)
19 #define CCM_SPCTL0 IO_ADDR_CCM(0xc)
20 #define CCM_SPCTL1 IO_ADDR_CCM(0x10)
21 #define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
22 #define CCM_PCDR0 IO_ADDR_CCM(0x18)
23 #define CCM_PCDR1 IO_ADDR_CCM(0x1c)
24 #define CCM_PCCR0 IO_ADDR_CCM(0x20)
25 #define CCM_PCCR1 IO_ADDR_CCM(0x24)
26 #define CCM_CCSR IO_ADDR_CCM(0x28)
27 #define CCM_PMCTL IO_ADDR_CCM(0x2c)
28 #define CCM_PMCOUNT IO_ADDR_CCM(0x30)
29 #define CCM_WKGDCTL IO_ADDR_CCM(0x34)
30
31 #define CCM_CSCR_UPDATE_DIS (1 << 31)
32 #define CCM_CSCR_SSI2 (1 << 23)
33 #define CCM_CSCR_SSI1 (1 << 22)
34 #define CCM_CSCR_VPU (1 << 21)
35 #define CCM_CSCR_MSHC (1 << 20)
36 #define CCM_CSCR_SPLLRES (1 << 19)
37 #define CCM_CSCR_MPLLRES (1 << 18)
38 #define CCM_CSCR_SP (1 << 17)
39 #define CCM_CSCR_MCU (1 << 16)
40 #define CCM_CSCR_OSC26MDIV (1 << 4)
41 #define CCM_CSCR_OSC26M (1 << 3)
42 #define CCM_CSCR_FPM (1 << 2)
43 #define CCM_CSCR_SPEN (1 << 1)
44 #define CCM_CSCR_MPEN (1 << 0)
45
46 /* i.MX27 TO 2+ */
47 #define CCM_CSCR_ARM_SRC (1 << 15)
48
49 #define CCM_SPCTL1_LF (1 << 15)
50 #define CCM_SPCTL1_BRMO (1 << 6)
51
52 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
53 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
54 static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
55 static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
56 static const char *clko_sel_clks[] = {
57 "ckil", "fpm", "ckih", "ckih",
58 "ckih", "mpll", "spll", "cpu_div",
59 "ahb", "ipg", "per1_div", "per2_div",
60 "per3_div", "per4_div", "ssi1_div", "ssi2_div",
61 "nfc_div", "mshc_div", "vpu_div", "60m",
62 "32k", "usb_div", "dptc",
63 };
64
65 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
66
67 enum mx27_clks {
68 dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
69 per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
70 clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
71 clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
72 sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
73 rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
74 kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
75 gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
76 gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
77 emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
78 cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
79 vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
80 usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
81 vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
82 csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
83 uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
84 uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
85 mpll_sel, spll_gate, clk_max
86 };
87
88 static struct clk *clk[clk_max];
89 static struct clk_onecell_data clk_data;
90
mx27_clocks_init(unsigned long fref)91 int __init mx27_clocks_init(unsigned long fref)
92 {
93 int i;
94 struct device_node *np;
95
96 clk[dummy] = imx_clk_fixed("dummy", 0);
97 clk[ckih] = imx_clk_fixed("ckih", fref);
98 clk[ckil] = imx_clk_fixed("ckil", 32768);
99 clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
100 clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
101
102 clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
103 mpll_osc_sel_clks,
104 ARRAY_SIZE(mpll_osc_sel_clks));
105 clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
106 ARRAY_SIZE(mpll_sel_clks));
107 clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
108 clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
109 clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
110 clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
111
112 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
113 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
114 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
115 } else {
116 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
117 clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
118 }
119
120 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
121 clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
122 clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
123 clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
124 clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
125 clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
126 clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
127 clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
128 clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
129 clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
130 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
131 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
132 else
133 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
134 clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
135 clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
136 clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
137 clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
138 clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
139 clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
140 clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
141 clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
142 clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
143 clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
144 clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
145 clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
146 clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
147 clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
148 clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
149 clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
150 clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
151 clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
152 clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
153 clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
154 clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
155 clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
156 clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
157 clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
158 clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
159 clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
160 clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
161 clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
162 clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
163 clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
164 clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
165 clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
166 clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
167 clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
168 clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
169 clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
170 clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
171 clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
172 clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
173 clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
174 clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
175 clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
176 clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
177 clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
178 clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
179 clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
180 clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
181 clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
182 clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
183 clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
184 clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
185 clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
186 clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
187 clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
188 clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
189 clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
190 clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
191 clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
192 clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
193 clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
194 clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
195 clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
196 clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
197
198 for (i = 0; i < ARRAY_SIZE(clk); i++)
199 if (IS_ERR(clk[i]))
200 pr_err("i.MX27 clk %d: register failed with %ld\n",
201 i, PTR_ERR(clk[i]));
202
203 np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
204 if (np) {
205 clk_data.clks = clk;
206 clk_data.clk_num = ARRAY_SIZE(clk);
207 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
208 }
209
210 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
211 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
212 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
213 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
214 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
215 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
216 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
217 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
218 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
219 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
220 clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
221 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
222 clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
223 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
224 clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
225 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
226 clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
227 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
228 clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
229 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
230 clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
231 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
232 clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
233 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
234 clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
235 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
236 clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
237 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
238 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
239 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
240 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
241 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
242 clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
243 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
244 clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
245 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
246 clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
247 clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
248 clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
249 clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
250 clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
251 clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
252 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
253 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
254 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
255 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
256 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
257 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
258 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
259 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
260 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
261 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
262 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
263 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
264 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
265 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
266 clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
267 clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
268 clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
269 clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
270 clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
271 clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
272 clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
273 clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
274 clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
275 clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
276 clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
277 clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
278 clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
279 clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
280 clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
281 clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
282 clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
283 clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
284 clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
285 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
286 clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
287 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
288 clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0");
289 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
290
291 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
292
293 clk_prepare_enable(clk[emi_ahb_gate]);
294
295 imx_print_silicon_rev("i.MX27", mx27_revision());
296
297 return 0;
298 }
299
300 #ifdef CONFIG_OF
mx27_clocks_init_dt(void)301 int __init mx27_clocks_init_dt(void)
302 {
303 struct device_node *np;
304 u32 fref = 26000000; /* default */
305
306 for_each_compatible_node(np, NULL, "fixed-clock") {
307 if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
308 continue;
309
310 if (!of_property_read_u32(np, "clock-frequency", &fref))
311 break;
312 }
313
314 return mx27_clocks_init(fref);
315 }
316 #endif
317