1 /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h 2 * 3 * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * S3C2410 GPIO register definitions 11 */ 12 13 14 #ifndef __ASM_ARCH_REGS_GPIO_H 15 #define __ASM_ARCH_REGS_GPIO_H 16 17 #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) 18 19 /* general configuration options */ 20 21 #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 22 #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ 23 #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) 24 #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ 25 #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ 26 #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ 27 28 /* register address for the GPIO registers. 29 * S3C24XX_GPIOREG2 is for the second set of registers in the 30 * GPIO which move between s3c2410 and s3c2412 type systems */ 31 32 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) 33 #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) 34 35 36 /* configure GPIO ports A..G */ 37 38 /* port A - S3C2410: 22bits, zero in bit X makes pin X output 39 * 1 makes port special function, this is default 40 */ 41 #define S3C2410_GPACON S3C2410_GPIOREG(0x00) 42 #define S3C2410_GPADAT S3C2410_GPIOREG(0x04) 43 44 #define S3C2410_GPA0_ADDR0 (1<<0) 45 #define S3C2410_GPA1_ADDR16 (1<<1) 46 #define S3C2410_GPA2_ADDR17 (1<<2) 47 #define S3C2410_GPA3_ADDR18 (1<<3) 48 #define S3C2410_GPA4_ADDR19 (1<<4) 49 #define S3C2410_GPA5_ADDR20 (1<<5) 50 #define S3C2410_GPA6_ADDR21 (1<<6) 51 #define S3C2410_GPA7_ADDR22 (1<<7) 52 #define S3C2410_GPA8_ADDR23 (1<<8) 53 #define S3C2410_GPA9_ADDR24 (1<<9) 54 #define S3C2410_GPA10_ADDR25 (1<<10) 55 #define S3C2410_GPA11_ADDR26 (1<<11) 56 #define S3C2410_GPA12_nGCS1 (1<<12) 57 #define S3C2410_GPA13_nGCS2 (1<<13) 58 #define S3C2410_GPA14_nGCS3 (1<<14) 59 #define S3C2410_GPA15_nGCS4 (1<<15) 60 #define S3C2410_GPA16_nGCS5 (1<<16) 61 #define S3C2410_GPA17_CLE (1<<17) 62 #define S3C2410_GPA18_ALE (1<<18) 63 #define S3C2410_GPA19_nFWE (1<<19) 64 #define S3C2410_GPA20_nFRE (1<<20) 65 #define S3C2410_GPA21_nRSTOUT (1<<21) 66 #define S3C2410_GPA22_nFCE (1<<22) 67 68 /* 0x08 and 0x0c are reserved on S3C2410 */ 69 70 /* S3C2410: 71 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. 72 * 00 = input, 01 = output, 10=special function, 11=reserved 73 74 * bit 0,1 = pin 0, 2,3= pin 1... 75 * 76 * CPBUP = pull up resistor control, 1=disabled, 0=enabled 77 */ 78 79 #define S3C2410_GPBCON S3C2410_GPIOREG(0x10) 80 #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) 81 #define S3C2410_GPBUP S3C2410_GPIOREG(0x18) 82 83 /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ 84 85 #define S3C2410_GPB0_TOUT0 (0x02 << 0) 86 87 #define S3C2410_GPB1_TOUT1 (0x02 << 2) 88 89 #define S3C2410_GPB2_TOUT2 (0x02 << 4) 90 91 #define S3C2410_GPB3_TOUT3 (0x02 << 6) 92 93 #define S3C2410_GPB4_TCLK0 (0x02 << 8) 94 #define S3C2410_GPB4_MASK (0x03 << 8) 95 96 #define S3C2410_GPB5_nXBACK (0x02 << 10) 97 #define S3C2443_GPB5_XBACK (0x03 << 10) 98 99 #define S3C2410_GPB6_nXBREQ (0x02 << 12) 100 #define S3C2443_GPB6_XBREQ (0x03 << 12) 101 102 #define S3C2410_GPB7_nXDACK1 (0x02 << 14) 103 #define S3C2443_GPB7_XDACK1 (0x03 << 14) 104 105 #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 106 107 #define S3C2410_GPB9_nXDACK0 (0x02 << 18) 108 #define S3C2443_GPB9_XDACK0 (0x03 << 18) 109 110 #define S3C2410_GPB10_nXDRE0 (0x02 << 20) 111 #define S3C2443_GPB10_XDREQ0 (0x03 << 20) 112 113 #define S3C2410_GPB_PUPDIS(x) (1<<(x)) 114 115 /* Port C consits of 16 GPIO/Special function 116 * 117 * almost identical setup to port b, but the special functions are mostly 118 * to do with the video system's sync/etc. 119 */ 120 121 #define S3C2410_GPCCON S3C2410_GPIOREG(0x20) 122 #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) 123 #define S3C2410_GPCUP S3C2410_GPIOREG(0x28) 124 #define S3C2410_GPC0_LEND (0x02 << 0) 125 #define S3C2410_GPC1_VCLK (0x02 << 2) 126 #define S3C2410_GPC2_VLINE (0x02 << 4) 127 #define S3C2410_GPC3_VFRAME (0x02 << 6) 128 #define S3C2410_GPC4_VM (0x02 << 8) 129 #define S3C2410_GPC5_LCDVF0 (0x02 << 10) 130 #define S3C2410_GPC6_LCDVF1 (0x02 << 12) 131 #define S3C2410_GPC7_LCDVF2 (0x02 << 14) 132 #define S3C2410_GPC8_VD0 (0x02 << 16) 133 #define S3C2410_GPC9_VD1 (0x02 << 18) 134 #define S3C2410_GPC10_VD2 (0x02 << 20) 135 #define S3C2410_GPC11_VD3 (0x02 << 22) 136 #define S3C2410_GPC12_VD4 (0x02 << 24) 137 #define S3C2410_GPC13_VD5 (0x02 << 26) 138 #define S3C2410_GPC14_VD6 (0x02 << 28) 139 #define S3C2410_GPC15_VD7 (0x02 << 30) 140 #define S3C2410_GPC_PUPDIS(x) (1<<(x)) 141 142 /* 143 * S3C2410: Port D consists of 16 GPIO/Special function 144 * 145 * almost identical setup to port b, but the special functions are mostly 146 * to do with the video system's data. 147 * 148 * almost identical setup to port c 149 */ 150 151 #define S3C2410_GPDCON S3C2410_GPIOREG(0x30) 152 #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) 153 #define S3C2410_GPDUP S3C2410_GPIOREG(0x38) 154 155 #define S3C2410_GPD0_VD8 (0x02 << 0) 156 #define S3C2442_GPD0_nSPICS1 (0x03 << 0) 157 158 #define S3C2410_GPD1_VD9 (0x02 << 2) 159 #define S3C2442_GPD1_SPICLK1 (0x03 << 2) 160 161 #define S3C2410_GPD2_VD10 (0x02 << 4) 162 163 #define S3C2410_GPD3_VD11 (0x02 << 6) 164 165 #define S3C2410_GPD4_VD12 (0x02 << 8) 166 167 #define S3C2410_GPD5_VD13 (0x02 << 10) 168 169 #define S3C2410_GPD6_VD14 (0x02 << 12) 170 171 #define S3C2410_GPD7_VD15 (0x02 << 14) 172 173 #define S3C2410_GPD8_VD16 (0x02 << 16) 174 #define S3C2440_GPD8_SPIMISO1 (0x03 << 16) 175 176 #define S3C2410_GPD9_VD17 (0x02 << 18) 177 #define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) 178 179 #define S3C2410_GPD10_VD18 (0x02 << 20) 180 #define S3C2440_GPD10_SPICLK1 (0x03 << 20) 181 182 #define S3C2410_GPD11_VD19 (0x02 << 22) 183 184 #define S3C2410_GPD12_VD20 (0x02 << 24) 185 186 #define S3C2410_GPD13_VD21 (0x02 << 26) 187 188 #define S3C2410_GPD14_VD22 (0x02 << 28) 189 #define S3C2410_GPD14_nSS1 (0x03 << 28) 190 191 #define S3C2410_GPD15_VD23 (0x02 << 30) 192 #define S3C2410_GPD15_nSS0 (0x03 << 30) 193 194 #define S3C2410_GPD_PUPDIS(x) (1<<(x)) 195 196 /* S3C2410: 197 * Port E consists of 16 GPIO/Special function 198 * 199 * again, the same as port B, but dealing with I2S, SDI, and 200 * more miscellaneous functions 201 * 202 * GPIO / interrupt inputs 203 */ 204 205 #define S3C2410_GPECON S3C2410_GPIOREG(0x40) 206 #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) 207 #define S3C2410_GPEUP S3C2410_GPIOREG(0x48) 208 209 #define S3C2410_GPE0_I2SLRCK (0x02 << 0) 210 #define S3C2443_GPE0_AC_nRESET (0x03 << 0) 211 #define S3C2410_GPE0_MASK (0x03 << 0) 212 213 #define S3C2410_GPE1_I2SSCLK (0x02 << 2) 214 #define S3C2443_GPE1_AC_SYNC (0x03 << 2) 215 #define S3C2410_GPE1_MASK (0x03 << 2) 216 217 #define S3C2410_GPE2_CDCLK (0x02 << 4) 218 #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) 219 220 #define S3C2410_GPE3_I2SSDI (0x02 << 6) 221 #define S3C2443_GPE3_AC_SDI (0x03 << 6) 222 #define S3C2410_GPE3_nSS0 (0x03 << 6) 223 #define S3C2410_GPE3_MASK (0x03 << 6) 224 225 #define S3C2410_GPE4_I2SSDO (0x02 << 8) 226 #define S3C2443_GPE4_AC_SDO (0x03 << 8) 227 #define S3C2410_GPE4_I2SSDI (0x03 << 8) 228 #define S3C2410_GPE4_MASK (0x03 << 8) 229 230 #define S3C2410_GPE5_SDCLK (0x02 << 10) 231 #define S3C2443_GPE5_SD1_CLK (0x02 << 10) 232 #define S3C2443_GPE5_AC_BITCLK (0x03 << 10) 233 234 #define S3C2410_GPE6_SDCMD (0x02 << 12) 235 #define S3C2443_GPE6_SD1_CMD (0x02 << 12) 236 #define S3C2443_GPE6_AC_SDI (0x03 << 12) 237 238 #define S3C2410_GPE7_SDDAT0 (0x02 << 14) 239 #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) 240 #define S3C2443_GPE7_AC_SDO (0x03 << 14) 241 242 #define S3C2410_GPE8_SDDAT1 (0x02 << 16) 243 #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) 244 #define S3C2443_GPE8_AC_SYNC (0x03 << 16) 245 246 #define S3C2410_GPE9_SDDAT2 (0x02 << 18) 247 #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) 248 #define S3C2443_GPE9_AC_nRESET (0x03 << 18) 249 250 #define S3C2410_GPE10_SDDAT3 (0x02 << 20) 251 #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) 252 253 #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 254 255 #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) 256 257 #define S3C2410_GPE13_SPICLK0 (0x02 << 26) 258 259 #define S3C2410_GPE14_IICSCL (0x02 << 28) 260 #define S3C2410_GPE14_MASK (0x03 << 28) 261 262 #define S3C2410_GPE15_IICSDA (0x02 << 30) 263 #define S3C2410_GPE15_MASK (0x03 << 30) 264 265 #define S3C2440_GPE0_ACSYNC (0x03 << 0) 266 #define S3C2440_GPE1_ACBITCLK (0x03 << 2) 267 #define S3C2440_GPE2_ACRESET (0x03 << 4) 268 #define S3C2440_GPE3_ACIN (0x03 << 6) 269 #define S3C2440_GPE4_ACOUT (0x03 << 8) 270 271 #define S3C2410_GPE_PUPDIS(x) (1<<(x)) 272 273 /* S3C2410: 274 * Port F consists of 8 GPIO/Special function 275 * 276 * GPIO / interrupt inputs 277 * 278 * GPFCON has 2 bits for each of the input pins on port F 279 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined 280 * 281 * pull up works like all other ports. 282 * 283 * GPIO/serial/misc pins 284 */ 285 286 #define S3C2410_GPFCON S3C2410_GPIOREG(0x50) 287 #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) 288 #define S3C2410_GPFUP S3C2410_GPIOREG(0x58) 289 290 #define S3C2410_GPF0_EINT0 (0x02 << 0) 291 #define S3C2410_GPF1_EINT1 (0x02 << 2) 292 #define S3C2410_GPF2_EINT2 (0x02 << 4) 293 #define S3C2410_GPF3_EINT3 (0x02 << 6) 294 #define S3C2410_GPF4_EINT4 (0x02 << 8) 295 #define S3C2410_GPF5_EINT5 (0x02 << 10) 296 #define S3C2410_GPF6_EINT6 (0x02 << 12) 297 #define S3C2410_GPF7_EINT7 (0x02 << 14) 298 #define S3C2410_GPF_PUPDIS(x) (1<<(x)) 299 300 /* S3C2410: 301 * Port G consists of 8 GPIO/IRQ/Special function 302 * 303 * GPGCON has 2 bits for each of the input pins on port G 304 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 305 * 306 * pull up works like all other ports. 307 */ 308 309 #define S3C2410_GPGCON S3C2410_GPIOREG(0x60) 310 #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) 311 #define S3C2410_GPGUP S3C2410_GPIOREG(0x68) 312 313 #define S3C2410_GPG0_EINT8 (0x02 << 0) 314 315 #define S3C2410_GPG1_EINT9 (0x02 << 2) 316 317 #define S3C2410_GPG2_EINT10 (0x02 << 4) 318 #define S3C2410_GPG2_nSS0 (0x03 << 4) 319 320 #define S3C2410_GPG3_EINT11 (0x02 << 6) 321 #define S3C2410_GPG3_nSS1 (0x03 << 6) 322 323 #define S3C2410_GPG4_EINT12 (0x02 << 8) 324 #define S3C2410_GPG4_LCDPWREN (0x03 << 8) 325 #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) 326 327 #define S3C2410_GPG5_EINT13 (0x02 << 10) 328 #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ 329 330 #define S3C2410_GPG6_EINT14 (0x02 << 12) 331 #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 332 333 #define S3C2410_GPG7_EINT15 (0x02 << 14) 334 #define S3C2410_GPG7_SPICLK1 (0x03 << 14) 335 336 #define S3C2410_GPG8_EINT16 (0x02 << 16) 337 338 #define S3C2410_GPG9_EINT17 (0x02 << 18) 339 340 #define S3C2410_GPG10_EINT18 (0x02 << 20) 341 342 #define S3C2410_GPG11_EINT19 (0x02 << 22) 343 #define S3C2410_GPG11_TCLK1 (0x03 << 22) 344 #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) 345 346 #define S3C2410_GPG12_EINT20 (0x02 << 24) 347 #define S3C2410_GPG12_XMON (0x03 << 24) 348 #define S3C2442_GPG12_nSPICS0 (0x03 << 24) 349 #define S3C2443_GPG12_nINPACK (0x03 << 24) 350 351 #define S3C2410_GPG13_EINT21 (0x02 << 26) 352 #define S3C2410_GPG13_nXPON (0x03 << 26) 353 #define S3C2443_GPG13_CF_nREG (0x03 << 26) 354 355 #define S3C2410_GPG14_EINT22 (0x02 << 28) 356 #define S3C2410_GPG14_YMON (0x03 << 28) 357 #define S3C2443_GPG14_CF_RESET (0x03 << 28) 358 359 #define S3C2410_GPG15_EINT23 (0x02 << 30) 360 #define S3C2410_GPG15_nYPON (0x03 << 30) 361 #define S3C2443_GPG15_CF_PWR (0x03 << 30) 362 363 #define S3C2410_GPG_PUPDIS(x) (1<<(x)) 364 365 /* Port H consists of11 GPIO/serial/Misc pins 366 * 367 * GPHCON has 2 bits for each of the input pins on port H 368 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 369 * 370 * pull up works like all other ports. 371 */ 372 373 #define S3C2410_GPHCON S3C2410_GPIOREG(0x70) 374 #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) 375 #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) 376 377 #define S3C2410_GPH0_nCTS0 (0x02 << 0) 378 #define S3C2416_GPH0_TXD0 (0x02 << 0) 379 380 #define S3C2410_GPH1_nRTS0 (0x02 << 2) 381 #define S3C2416_GPH1_RXD0 (0x02 << 2) 382 383 #define S3C2410_GPH2_TXD0 (0x02 << 4) 384 #define S3C2416_GPH2_TXD1 (0x02 << 4) 385 386 #define S3C2410_GPH3_RXD0 (0x02 << 6) 387 #define S3C2416_GPH3_RXD1 (0x02 << 6) 388 389 #define S3C2410_GPH4_TXD1 (0x02 << 8) 390 #define S3C2416_GPH4_TXD2 (0x02 << 8) 391 392 #define S3C2410_GPH5_RXD1 (0x02 << 10) 393 #define S3C2416_GPH5_RXD2 (0x02 << 10) 394 395 #define S3C2410_GPH6_TXD2 (0x02 << 12) 396 #define S3C2416_GPH6_TXD3 (0x02 << 12) 397 #define S3C2410_GPH6_nRTS1 (0x03 << 12) 398 #define S3C2416_GPH6_nRTS2 (0x03 << 12) 399 400 #define S3C2410_GPH7_RXD2 (0x02 << 14) 401 #define S3C2416_GPH7_RXD3 (0x02 << 14) 402 #define S3C2410_GPH7_nCTS1 (0x03 << 14) 403 #define S3C2416_GPH7_nCTS2 (0x03 << 14) 404 405 #define S3C2410_GPH8_UCLK (0x02 << 16) 406 #define S3C2416_GPH8_nCTS0 (0x02 << 16) 407 408 #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 409 #define S3C2442_GPH9_nSPICS0 (0x03 << 18) 410 #define S3C2416_GPH9_nRTS0 (0x02 << 18) 411 412 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 413 #define S3C2416_GPH10_nCTS1 (0x02 << 20) 414 415 #define S3C2416_GPH11_nRTS1 (0x02 << 22) 416 417 #define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) 418 419 #define S3C2416_GPH13_CLKOUT0 (0x02 << 26) 420 421 #define S3C2416_GPH14_CLKOUT1 (0x02 << 28) 422 423 /* The S3C2412 and S3C2413 move the GPJ register set to after 424 * GPH, which means all registers after 0x80 are now offset by 0x10 425 * for the 2412/2413 from the 2410/2440/2442 426 */ 427 428 /* 429 * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits 430 * for each of the pins on port J. 431 * 00 - input, 01 output, 10 - camera 432 * 433 * Pull up works like all other ports. 434 */ 435 436 #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) 437 #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) 438 #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) 439 #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) 440 441 /* S3C2443 and above */ 442 #define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) 443 #define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) 444 #define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) 445 446 #define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) 447 #define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) 448 #define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) 449 450 #define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) 451 #define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) 452 #define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) 453 454 #define S3C2443_GPMCON S3C2410_GPIOREG(0x100) 455 #define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) 456 #define S3C2443_GPMUP S3C2410_GPIOREG(0x108) 457 458 /* miscellaneous control */ 459 #define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 460 #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) 461 462 #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) 463 464 /* see clock.h for dclk definitions */ 465 466 /* pullup control on databus */ 467 #define S3C2410_MISCCR_SPUCR_HEN (0<<0) 468 #define S3C2410_MISCCR_SPUCR_HDIS (1<<0) 469 #define S3C2410_MISCCR_SPUCR_LEN (0<<1) 470 #define S3C2410_MISCCR_SPUCR_LDIS (1<<1) 471 472 #define S3C2410_MISCCR_USBDEV (0<<3) 473 #define S3C2410_MISCCR_USBHOST (1<<3) 474 475 #define S3C2410_MISCCR_CLK0_MPLL (0<<4) 476 #define S3C2410_MISCCR_CLK0_UPLL (1<<4) 477 #define S3C2410_MISCCR_CLK0_FCLK (2<<4) 478 #define S3C2410_MISCCR_CLK0_HCLK (3<<4) 479 #define S3C2410_MISCCR_CLK0_PCLK (4<<4) 480 #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) 481 #define S3C2410_MISCCR_CLK0_MASK (7<<4) 482 483 #define S3C2412_MISCCR_CLK0_RTC (2<<4) 484 485 #define S3C2410_MISCCR_CLK1_MPLL (0<<8) 486 #define S3C2410_MISCCR_CLK1_UPLL (1<<8) 487 #define S3C2410_MISCCR_CLK1_FCLK (2<<8) 488 #define S3C2410_MISCCR_CLK1_HCLK (3<<8) 489 #define S3C2410_MISCCR_CLK1_PCLK (4<<8) 490 #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) 491 #define S3C2410_MISCCR_CLK1_MASK (7<<8) 492 493 #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) 494 495 #define S3C2410_MISCCR_USBSUSPND0 (1<<12) 496 #define S3C2416_MISCCR_SEL_SUSPND (1<<12) 497 #define S3C2410_MISCCR_USBSUSPND1 (1<<13) 498 499 #define S3C2410_MISCCR_nRSTCON (1<<16) 500 501 #define S3C2410_MISCCR_nEN_SCLK0 (1<<17) 502 #define S3C2410_MISCCR_nEN_SCLK1 (1<<18) 503 #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ 504 #define S3C2410_MISCCR_SDSLEEP (7<<17) 505 506 #define S3C2416_MISCCR_FLT_I2C (1<<24) 507 #define S3C2416_MISCCR_HSSPI_EN2 (1<<31) 508 509 /* external interrupt control... */ 510 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 511 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 512 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 513 * 514 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 515 * 516 * Samsung datasheet p9-25 517 */ 518 #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) 519 #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 520 #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 521 522 #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) 523 #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) 524 #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) 525 526 /* interrupt filtering conrrol for EINT16..EINT23 */ 527 #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) 528 #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) 529 #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) 530 #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) 531 532 #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) 533 #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) 534 #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) 535 #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) 536 537 /* values for interrupt filtering */ 538 #define S3C2410_EINTFLT_PCLK (0x00) 539 #define S3C2410_EINTFLT_EXTCLK (1<<7) 540 #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) 541 542 /* removed EINTxxxx defs from here, not meant for this */ 543 544 /* GSTATUS have miscellaneous information in them 545 * 546 * These move between s3c2410 and s3c2412 style systems. 547 */ 548 549 #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) 550 #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) 551 #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) 552 #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) 553 #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) 554 555 #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) 556 #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) 557 #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) 558 #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) 559 #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) 560 561 #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) 562 #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) 563 #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) 564 #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) 565 #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) 566 567 #define S3C2410_GSTATUS0_nWAIT (1<<3) 568 #define S3C2410_GSTATUS0_NCON (1<<2) 569 #define S3C2410_GSTATUS0_RnB (1<<1) 570 #define S3C2410_GSTATUS0_nBATTFLT (1<<0) 571 572 #define S3C2410_GSTATUS1_IDMASK (0xffff0000) 573 #define S3C2410_GSTATUS1_2410 (0x32410000) 574 #define S3C2410_GSTATUS1_2412 (0x32412001) 575 #define S3C2410_GSTATUS1_2416 (0x32416003) 576 #define S3C2410_GSTATUS1_2440 (0x32440000) 577 #define S3C2410_GSTATUS1_2442 (0x32440aaa) 578 /* some 2416 CPUs report this value also */ 579 #define S3C2410_GSTATUS1_2450 (0x32450003) 580 581 #define S3C2410_GSTATUS2_WTRESET (1<<2) 582 #define S3C2410_GSTATUS2_OFFRESET (1<<1) 583 #define S3C2410_GSTATUS2_PONRESET (1<<0) 584 585 /* 2412/2413 sleep configuration registers */ 586 587 #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) 588 #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) 589 #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) 590 #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) 591 #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) 592 #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) 593 594 /* definitions for each pin bit */ 595 #define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) 596 #define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) 597 #define S3C2412_GPIO_SLPCON_IN ( 0x02 ) 598 #define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) 599 600 #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) 601 #define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) 602 #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) 603 #define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) 604 #define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ 605 #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) 606 607 #define S3C2412_SLPCON_ALL_LOW (0x0) 608 #define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) 609 #define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) 610 #define S3C2412_SLPCON_ALL_PULL (0x33333333) 611 612 #endif /* __ASM_ARCH_REGS_GPIO_H */ 613 614