1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Parts of this file are based on Ralink's 2.6.21 BSP 7 * 8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 11 */ 12 13 #ifndef _MT7620_REGS_H_ 14 #define _MT7620_REGS_H_ 15 16 #define MT7620_SYSC_BASE 0x10000000 17 18 #define SYSC_REG_CHIP_NAME0 0x00 19 #define SYSC_REG_CHIP_NAME1 0x04 20 #define SYSC_REG_CHIP_REV 0x0c 21 #define SYSC_REG_SYSTEM_CONFIG0 0x10 22 #define SYSC_REG_SYSTEM_CONFIG1 0x14 23 #define SYSC_REG_CPLL_CONFIG0 0x54 24 #define SYSC_REG_CPLL_CONFIG1 0x58 25 26 #define MT7620N_CHIP_NAME0 0x33365452 27 #define MT7620N_CHIP_NAME1 0x20203235 28 29 #define MT7620A_CHIP_NAME0 0x3637544d 30 #define MT7620A_CHIP_NAME1 0x20203032 31 32 #define CHIP_REV_PKG_MASK 0x1 33 #define CHIP_REV_PKG_SHIFT 16 34 #define CHIP_REV_VER_MASK 0xf 35 #define CHIP_REV_VER_SHIFT 8 36 #define CHIP_REV_ECO_MASK 0xf 37 38 #define CPLL_SW_CONFIG_SHIFT 31 39 #define CPLL_SW_CONFIG_MASK 0x1 40 #define CPLL_CPU_CLK_SHIFT 24 41 #define CPLL_CPU_CLK_MASK 0x1 42 #define CPLL_MULT_RATIO_SHIFT 16 43 #define CPLL_MULT_RATIO 0x7 44 #define CPLL_DIV_RATIO_SHIFT 10 45 #define CPLL_DIV_RATIO 0x3 46 47 #define SYSCFG0_DRAM_TYPE_MASK 0x3 48 #define SYSCFG0_DRAM_TYPE_SHIFT 4 49 #define SYSCFG0_DRAM_TYPE_SDRAM 0 50 #define SYSCFG0_DRAM_TYPE_DDR1 1 51 #define SYSCFG0_DRAM_TYPE_DDR2 2 52 53 #define MT7620_DRAM_BASE 0x0 54 #define MT7620_SDRAM_SIZE_MIN 2 55 #define MT7620_SDRAM_SIZE_MAX 64 56 #define MT7620_DDR1_SIZE_MIN 32 57 #define MT7620_DDR1_SIZE_MAX 128 58 #define MT7620_DDR2_SIZE_MIN 32 59 #define MT7620_DDR2_SIZE_MAX 256 60 61 #define MT7620_GPIO_MODE_I2C BIT(0) 62 #define MT7620_GPIO_MODE_UART0_SHIFT 2 63 #define MT7620_GPIO_MODE_UART0_MASK 0x7 64 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) 65 #define MT7620_GPIO_MODE_UARTF 0x0 66 #define MT7620_GPIO_MODE_PCM_UARTF 0x1 67 #define MT7620_GPIO_MODE_PCM_I2S 0x2 68 #define MT7620_GPIO_MODE_I2S_UARTF 0x3 69 #define MT7620_GPIO_MODE_PCM_GPIO 0x4 70 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5 71 #define MT7620_GPIO_MODE_GPIO_I2S 0x6 72 #define MT7620_GPIO_MODE_GPIO 0x7 73 #define MT7620_GPIO_MODE_UART1 BIT(5) 74 #define MT7620_GPIO_MODE_MDIO BIT(8) 75 #define MT7620_GPIO_MODE_RGMII1 BIT(9) 76 #define MT7620_GPIO_MODE_RGMII2 BIT(10) 77 #define MT7620_GPIO_MODE_SPI BIT(11) 78 #define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12) 79 #define MT7620_GPIO_MODE_WLED BIT(13) 80 #define MT7620_GPIO_MODE_JTAG BIT(15) 81 #define MT7620_GPIO_MODE_EPHY BIT(15) 82 #define MT7620_GPIO_MODE_WDT BIT(22) 83 84 #endif 85