1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 * Copyright (C) 2011 MIPS Technologies, Inc.
13 *
14 * ... and the days got worse and worse and now you see
15 * I've gone completly out of my mind.
16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
22 */
23
24 #include <linux/bug.h>
25 #include <linux/kernel.h>
26 #include <linux/types.h>
27 #include <linux/smp.h>
28 #include <linux/string.h>
29 #include <linux/init.h>
30 #include <linux/cache.h>
31
32 #include <asm/cacheflush.h>
33 #include <asm/pgtable.h>
34 #include <asm/war.h>
35 #include <asm/uasm.h>
36 #include <asm/setup.h>
37
38 /*
39 * TLB load/store/modify handlers.
40 *
41 * Only the fastpath gets synthesized at runtime, the slowpath for
42 * do_page_fault remains normal asm.
43 */
44 extern void tlb_do_page_fault_0(void);
45 extern void tlb_do_page_fault_1(void);
46
47 struct work_registers {
48 int r1;
49 int r2;
50 int r3;
51 };
52
53 struct tlb_reg_save {
54 unsigned long a;
55 unsigned long b;
56 } ____cacheline_aligned_in_smp;
57
58 static struct tlb_reg_save handler_reg_save[NR_CPUS * 2];
59
r45k_bvahwbug(void)60 static inline int r45k_bvahwbug(void)
61 {
62 /* XXX: We should probe for the presence of this bug, but we don't. */
63 return 0;
64 }
65
r4k_250MHZhwbug(void)66 static inline int r4k_250MHZhwbug(void)
67 {
68 /* XXX: We should probe for the presence of this bug, but we don't. */
69 return 0;
70 }
71
bcm1250_m3_war(void)72 static inline int __maybe_unused bcm1250_m3_war(void)
73 {
74 return BCM1250_M3_WAR;
75 }
76
r10000_llsc_war(void)77 static inline int __maybe_unused r10000_llsc_war(void)
78 {
79 return R10000_LLSC_WAR;
80 }
81
use_bbit_insns(void)82 static int use_bbit_insns(void)
83 {
84 switch (current_cpu_type()) {
85 case CPU_CAVIUM_OCTEON:
86 case CPU_CAVIUM_OCTEON_PLUS:
87 case CPU_CAVIUM_OCTEON2:
88 return 1;
89 default:
90 return 0;
91 }
92 }
93
use_lwx_insns(void)94 static int use_lwx_insns(void)
95 {
96 switch (current_cpu_type()) {
97 case CPU_CAVIUM_OCTEON2:
98 return 1;
99 default:
100 return 0;
101 }
102 }
103 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
104 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
scratchpad_available(void)105 static bool scratchpad_available(void)
106 {
107 return true;
108 }
scratchpad_offset(int i)109 static int scratchpad_offset(int i)
110 {
111 /*
112 * CVMSEG starts at address -32768 and extends for
113 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
114 */
115 i += 1; /* Kernel use starts at the top and works down. */
116 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
117 }
118 #else
scratchpad_available(void)119 static bool scratchpad_available(void)
120 {
121 return false;
122 }
scratchpad_offset(int i)123 static int scratchpad_offset(int i)
124 {
125 BUG();
126 /* Really unreachable, but evidently some GCC want this. */
127 return 0;
128 }
129 #endif
130 /*
131 * Found by experiment: At least some revisions of the 4kc throw under
132 * some circumstances a machine check exception, triggered by invalid
133 * values in the index register. Delaying the tlbp instruction until
134 * after the next branch, plus adding an additional nop in front of
135 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
136 * why; it's not an issue caused by the core RTL.
137 *
138 */
m4kc_tlbp_war(void)139 static int __cpuinit m4kc_tlbp_war(void)
140 {
141 return (current_cpu_data.processor_id & 0xffff00) ==
142 (PRID_COMP_MIPS | PRID_IMP_4KC);
143 }
144
145 /* Handle labels (which must be positive integers). */
146 enum label_id {
147 label_second_part = 1,
148 label_leave,
149 label_vmalloc,
150 label_vmalloc_done,
151 label_tlbw_hazard_0,
152 label_split = label_tlbw_hazard_0 + 8,
153 label_tlbl_goaround1,
154 label_tlbl_goaround2,
155 label_nopage_tlbl,
156 label_nopage_tlbs,
157 label_nopage_tlbm,
158 label_smp_pgtable_change,
159 label_r3000_write_probe_fail,
160 label_large_segbits_fault,
161 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
162 label_tlb_huge_update,
163 #endif
164 };
165
166 UASM_L_LA(_second_part)
167 UASM_L_LA(_leave)
168 UASM_L_LA(_vmalloc)
169 UASM_L_LA(_vmalloc_done)
170 /* _tlbw_hazard_x is handled differently. */
171 UASM_L_LA(_split)
172 UASM_L_LA(_tlbl_goaround1)
173 UASM_L_LA(_tlbl_goaround2)
174 UASM_L_LA(_nopage_tlbl)
175 UASM_L_LA(_nopage_tlbs)
176 UASM_L_LA(_nopage_tlbm)
177 UASM_L_LA(_smp_pgtable_change)
178 UASM_L_LA(_r3000_write_probe_fail)
179 UASM_L_LA(_large_segbits_fault)
180 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
181 UASM_L_LA(_tlb_huge_update)
182 #endif
183
184 static int __cpuinitdata hazard_instance;
185
uasm_bgezl_hazard(u32 ** p,struct uasm_reloc ** r,int instance)186 static void __cpuinit uasm_bgezl_hazard(u32 **p,
187 struct uasm_reloc **r,
188 int instance)
189 {
190 switch (instance) {
191 case 0 ... 7:
192 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
193 return;
194 default:
195 BUG();
196 }
197 }
198
uasm_bgezl_label(struct uasm_label ** l,u32 ** p,int instance)199 static void __cpuinit uasm_bgezl_label(struct uasm_label **l,
200 u32 **p,
201 int instance)
202 {
203 switch (instance) {
204 case 0 ... 7:
205 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
206 break;
207 default:
208 BUG();
209 }
210 }
211
212 /*
213 * pgtable bits are assigned dynamically depending on processor feature
214 * and statically based on kernel configuration. This spits out the actual
215 * values the kernel is using. Required to make sense from disassembled
216 * TLB exception handlers.
217 */
output_pgtable_bits_defines(void)218 static void output_pgtable_bits_defines(void)
219 {
220 #define pr_define(fmt, ...) \
221 pr_debug("#define " fmt, ##__VA_ARGS__)
222
223 pr_debug("#include <asm/asm.h>\n");
224 pr_debug("#include <asm/regdef.h>\n");
225 pr_debug("\n");
226
227 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
228 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT);
229 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
230 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
231 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
232 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
233 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
234 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT);
235 #endif
236 if (cpu_has_rixi) {
237 #ifdef _PAGE_NO_EXEC_SHIFT
238 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
239 #endif
240 #ifdef _PAGE_NO_READ_SHIFT
241 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
242 #endif
243 }
244 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
245 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
246 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
247 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
248 pr_debug("\n");
249 }
250
dump_handler(const char * symbol,const u32 * handler,int count)251 static inline void dump_handler(const char *symbol, const u32 *handler, int count)
252 {
253 int i;
254
255 pr_debug("LEAF(%s)\n", symbol);
256
257 pr_debug("\t.set push\n");
258 pr_debug("\t.set noreorder\n");
259
260 for (i = 0; i < count; i++)
261 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
262
263 pr_debug("\t.set\tpop\n");
264
265 pr_debug("\tEND(%s)\n", symbol);
266 }
267
268 /* The only general purpose registers allowed in TLB handlers. */
269 #define K0 26
270 #define K1 27
271
272 /* Some CP0 registers */
273 #define C0_INDEX 0, 0
274 #define C0_ENTRYLO0 2, 0
275 #define C0_TCBIND 2, 2
276 #define C0_ENTRYLO1 3, 0
277 #define C0_CONTEXT 4, 0
278 #define C0_PAGEMASK 5, 0
279 #define C0_BADVADDR 8, 0
280 #define C0_ENTRYHI 10, 0
281 #define C0_EPC 14, 0
282 #define C0_XCONTEXT 20, 0
283
284 #ifdef CONFIG_64BIT
285 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
286 #else
287 # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
288 #endif
289
290 /* The worst case length of the handler is around 18 instructions for
291 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
292 * Maximum space available is 32 instructions for R3000 and 64
293 * instructions for R4000.
294 *
295 * We deliberately chose a buffer size of 128, so we won't scribble
296 * over anything important on overflow before we panic.
297 */
298 static u32 tlb_handler[128] __cpuinitdata;
299
300 /* simply assume worst case size for labels and relocs */
301 static struct uasm_label labels[128] __cpuinitdata;
302 static struct uasm_reloc relocs[128] __cpuinitdata;
303
304 static int check_for_high_segbits __cpuinitdata;
305
306 static unsigned int kscratch_used_mask __cpuinitdata;
307
allocate_kscratch(void)308 static int __cpuinit allocate_kscratch(void)
309 {
310 int r;
311 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
312
313 r = ffs(a);
314
315 if (r == 0)
316 return -1;
317
318 r--; /* make it zero based */
319
320 kscratch_used_mask |= (1 << r);
321
322 return r;
323 }
324
325 static int scratch_reg __cpuinitdata;
326 static int pgd_reg __cpuinitdata;
327 enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
328
build_get_work_registers(u32 ** p)329 static struct work_registers __cpuinit build_get_work_registers(u32 **p)
330 {
331 struct work_registers r;
332
333 int smp_processor_id_reg;
334 int smp_processor_id_sel;
335 int smp_processor_id_shift;
336
337 if (scratch_reg > 0) {
338 /* Save in CPU local C0_KScratch? */
339 UASM_i_MTC0(p, 1, 31, scratch_reg);
340 r.r1 = K0;
341 r.r2 = K1;
342 r.r3 = 1;
343 return r;
344 }
345
346 if (num_possible_cpus() > 1) {
347 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
348 smp_processor_id_shift = 51;
349 smp_processor_id_reg = 20; /* XContext */
350 smp_processor_id_sel = 0;
351 #else
352 # ifdef CONFIG_32BIT
353 smp_processor_id_shift = 25;
354 smp_processor_id_reg = 4; /* Context */
355 smp_processor_id_sel = 0;
356 # endif
357 # ifdef CONFIG_64BIT
358 smp_processor_id_shift = 26;
359 smp_processor_id_reg = 4; /* Context */
360 smp_processor_id_sel = 0;
361 # endif
362 #endif
363 /* Get smp_processor_id */
364 UASM_i_MFC0(p, K0, smp_processor_id_reg, smp_processor_id_sel);
365 UASM_i_SRL_SAFE(p, K0, K0, smp_processor_id_shift);
366
367 /* handler_reg_save index in K0 */
368 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
369
370 UASM_i_LA(p, K1, (long)&handler_reg_save);
371 UASM_i_ADDU(p, K0, K0, K1);
372 } else {
373 UASM_i_LA(p, K0, (long)&handler_reg_save);
374 }
375 /* K0 now points to save area, save $1 and $2 */
376 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
377 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
378
379 r.r1 = K1;
380 r.r2 = 1;
381 r.r3 = 2;
382 return r;
383 }
384
build_restore_work_registers(u32 ** p)385 static void __cpuinit build_restore_work_registers(u32 **p)
386 {
387 if (scratch_reg > 0) {
388 UASM_i_MFC0(p, 1, 31, scratch_reg);
389 return;
390 }
391 /* K0 already points to save area, restore $1 and $2 */
392 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
393 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
394 }
395
396 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
397
398 /*
399 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
400 * we cannot do r3000 under these circumstances.
401 *
402 * Declare pgd_current here instead of including mmu_context.h to avoid type
403 * conflicts for tlbmiss_handler_setup_pgd
404 */
405 extern unsigned long pgd_current[];
406
407 /*
408 * The R3000 TLB handler is simple.
409 */
build_r3000_tlb_refill_handler(void)410 static void __cpuinit build_r3000_tlb_refill_handler(void)
411 {
412 long pgdc = (long)pgd_current;
413 u32 *p;
414
415 memset(tlb_handler, 0, sizeof(tlb_handler));
416 p = tlb_handler;
417
418 uasm_i_mfc0(&p, K0, C0_BADVADDR);
419 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
420 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
421 uasm_i_srl(&p, K0, K0, 22); /* load delay */
422 uasm_i_sll(&p, K0, K0, 2);
423 uasm_i_addu(&p, K1, K1, K0);
424 uasm_i_mfc0(&p, K0, C0_CONTEXT);
425 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
426 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
427 uasm_i_addu(&p, K1, K1, K0);
428 uasm_i_lw(&p, K0, 0, K1);
429 uasm_i_nop(&p); /* load delay */
430 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
431 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
432 uasm_i_tlbwr(&p); /* cp0 delay */
433 uasm_i_jr(&p, K1);
434 uasm_i_rfe(&p); /* branch delay */
435
436 if (p > tlb_handler + 32)
437 panic("TLB refill handler space exceeded");
438
439 pr_debug("Wrote TLB refill handler (%u instructions).\n",
440 (unsigned int)(p - tlb_handler));
441
442 memcpy((void *)ebase, tlb_handler, 0x80);
443 local_flush_icache_range(ebase, ebase + 0x80);
444
445 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
446 }
447 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
448
449 /*
450 * The R4000 TLB handler is much more complicated. We have two
451 * consecutive handler areas with 32 instructions space each.
452 * Since they aren't used at the same time, we can overflow in the
453 * other one.To keep things simple, we first assume linear space,
454 * then we relocate it to the final handler layout as needed.
455 */
456 static u32 final_handler[64] __cpuinitdata;
457
458 /*
459 * Hazards
460 *
461 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
462 * 2. A timing hazard exists for the TLBP instruction.
463 *
464 * stalling_instruction
465 * TLBP
466 *
467 * The JTLB is being read for the TLBP throughout the stall generated by the
468 * previous instruction. This is not really correct as the stalling instruction
469 * can modify the address used to access the JTLB. The failure symptom is that
470 * the TLBP instruction will use an address created for the stalling instruction
471 * and not the address held in C0_ENHI and thus report the wrong results.
472 *
473 * The software work-around is to not allow the instruction preceding the TLBP
474 * to stall - make it an NOP or some other instruction guaranteed not to stall.
475 *
476 * Errata 2 will not be fixed. This errata is also on the R5000.
477 *
478 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
479 */
build_tlb_probe_entry(u32 ** p)480 static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
481 {
482 switch (current_cpu_type()) {
483 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
484 case CPU_R4600:
485 case CPU_R4700:
486 case CPU_R5000:
487 case CPU_NEVADA:
488 uasm_i_nop(p);
489 uasm_i_tlbp(p);
490 break;
491
492 default:
493 uasm_i_tlbp(p);
494 break;
495 }
496 }
497
498 /*
499 * Write random or indexed TLB entry, and care about the hazards from
500 * the preceding mtc0 and for the following eret.
501 */
502 enum tlb_write_entry { tlb_random, tlb_indexed };
503
build_tlb_write_entry(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,enum tlb_write_entry wmode)504 static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
505 struct uasm_reloc **r,
506 enum tlb_write_entry wmode)
507 {
508 void(*tlbw)(u32 **) = NULL;
509
510 switch (wmode) {
511 case tlb_random: tlbw = uasm_i_tlbwr; break;
512 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
513 }
514
515 if (cpu_has_mips_r2 || cpu_has_mips_r6) {
516 /*
517 * The architecture spec says an ehb is required here,
518 * but a number of cores do not have the hazard and
519 * using an ehb causes an expensive pipeline stall.
520 */
521 if (cpu_has_mips_r2_exec_hazard) {
522 switch (current_cpu_type()) {
523 case CPU_M14KC:
524 case CPU_M14KEC:
525 case CPU_74K:
526 case CPU_PROAPTIV:
527 case CPU_INTERAPTIV:
528 case CPU_VIRTUOSO:
529 case CPU_P5600:
530 case CPU_SAMURAI:
531 break;
532
533 default:
534 uasm_i_ehb(p);
535 break;
536 }
537 }
538 tlbw(p);
539 return;
540 }
541
542 switch (current_cpu_type()) {
543 case CPU_R4000PC:
544 case CPU_R4000SC:
545 case CPU_R4000MC:
546 case CPU_R4400PC:
547 case CPU_R4400SC:
548 case CPU_R4400MC:
549 /*
550 * This branch uses up a mtc0 hazard nop slot and saves
551 * two nops after the tlbw instruction.
552 */
553 uasm_bgezl_hazard(p, r, hazard_instance);
554 tlbw(p);
555 uasm_bgezl_label(l, p, hazard_instance);
556 hazard_instance++;
557 uasm_i_nop(p);
558 break;
559
560 case CPU_R4600:
561 case CPU_R4700:
562 uasm_i_nop(p);
563 tlbw(p);
564 uasm_i_nop(p);
565 break;
566
567 case CPU_R5000:
568 case CPU_NEVADA:
569 uasm_i_nop(p); /* QED specifies 2 nops hazard */
570 uasm_i_nop(p); /* QED specifies 2 nops hazard */
571 tlbw(p);
572 break;
573
574 case CPU_R4300:
575 case CPU_5KC:
576 case CPU_TX49XX:
577 case CPU_PR4450:
578 case CPU_XLR:
579 uasm_i_nop(p);
580 tlbw(p);
581 break;
582
583 case CPU_R10000:
584 case CPU_R12000:
585 case CPU_R14000:
586 case CPU_4KC:
587 case CPU_4KEC:
588 case CPU_M14KC:
589 case CPU_M14KEC:
590 case CPU_SB1:
591 case CPU_SB1A:
592 case CPU_4KSC:
593 case CPU_20KC:
594 case CPU_25KF:
595 case CPU_BMIPS32:
596 case CPU_BMIPS3300:
597 case CPU_BMIPS4350:
598 case CPU_BMIPS4380:
599 case CPU_BMIPS5000:
600 case CPU_LOONGSON2:
601 case CPU_R5500:
602 if (m4kc_tlbp_war())
603 uasm_i_nop(p);
604 case CPU_ALCHEMY:
605 tlbw(p);
606 break;
607
608 case CPU_RM7000:
609 uasm_i_nop(p);
610 uasm_i_nop(p);
611 uasm_i_nop(p);
612 uasm_i_nop(p);
613 tlbw(p);
614 break;
615
616 case CPU_VR4111:
617 case CPU_VR4121:
618 case CPU_VR4122:
619 case CPU_VR4181:
620 case CPU_VR4181A:
621 uasm_i_nop(p);
622 uasm_i_nop(p);
623 tlbw(p);
624 uasm_i_nop(p);
625 uasm_i_nop(p);
626 break;
627
628 case CPU_VR4131:
629 case CPU_VR4133:
630 case CPU_R5432:
631 uasm_i_nop(p);
632 uasm_i_nop(p);
633 tlbw(p);
634 break;
635
636 case CPU_JZRISC:
637 tlbw(p);
638 uasm_i_nop(p);
639 break;
640
641 default:
642 panic("No TLB refill handler yet (CPU type: %d)",
643 current_cpu_data.cputype);
644 break;
645 }
646 }
647
build_convert_pte_to_entrylo(u32 ** p,unsigned int reg)648 static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
649 unsigned int reg)
650 {
651 if (cpu_has_rixi) {
652 if (!cpu_has_himem)
653 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
654 else {
655 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
656 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
657 }
658 } else {
659 #ifdef CONFIG_64BIT_PHYS_ADDR
660 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
661 #else
662 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
663 #endif
664 }
665 }
666
667 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
668
build_restore_pagemask(u32 ** p,struct uasm_reloc ** r,unsigned int tmp,enum label_id lid,int restore_scratch)669 static __cpuinit void build_restore_pagemask(u32 **p,
670 struct uasm_reloc **r,
671 unsigned int tmp,
672 enum label_id lid,
673 int restore_scratch)
674 {
675 if (restore_scratch) {
676 /* Reset default page size */
677 if (PM_DEFAULT_MASK >> 16) {
678 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
679 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
680 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
681 uasm_il_b(p, r, lid);
682 } else if (PM_DEFAULT_MASK) {
683 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
684 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
685 uasm_il_b(p, r, lid);
686 } else {
687 uasm_i_mtc0(p, 0, C0_PAGEMASK);
688 uasm_il_b(p, r, lid);
689 }
690 if (scratch_reg > 0)
691 UASM_i_MFC0(p, 1, 31, scratch_reg);
692 else
693 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
694 } else {
695 /* Reset default page size */
696 if (PM_DEFAULT_MASK >> 16) {
697 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
698 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
699 uasm_il_b(p, r, lid);
700 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
701 } else if (PM_DEFAULT_MASK) {
702 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
703 uasm_il_b(p, r, lid);
704 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
705 } else {
706 uasm_il_b(p, r, lid);
707 uasm_i_mtc0(p, 0, C0_PAGEMASK);
708 }
709 }
710 }
711
build_huge_tlb_write_entry(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,enum tlb_write_entry wmode,int restore_scratch)712 static __cpuinit void build_huge_tlb_write_entry(u32 **p,
713 struct uasm_label **l,
714 struct uasm_reloc **r,
715 unsigned int tmp,
716 enum tlb_write_entry wmode,
717 int restore_scratch)
718 {
719 /* Set huge page tlb entry size */
720 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
721 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
722 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
723
724 build_tlb_write_entry(p, l, r, wmode);
725
726 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
727 }
728
729 /*
730 * Check if Huge PTE is present, if so then jump to LABEL.
731 */
732 static void __cpuinit
build_is_huge_pte(u32 ** p,struct uasm_reloc ** r,unsigned int tmp,unsigned int pmd,int lid)733 build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
734 unsigned int pmd, int lid)
735 {
736 UASM_i_LW(p, tmp, 0, pmd);
737 if (use_bbit_insns()) {
738 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
739 } else {
740 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
741 uasm_il_bnez(p, r, tmp, lid);
742 }
743 }
744
build_huge_update_entries(u32 ** p,unsigned int pte,unsigned int tmp)745 static __cpuinit void build_huge_update_entries(u32 **p,
746 unsigned int pte,
747 unsigned int tmp)
748 {
749 int small_sequence;
750
751 /*
752 * A huge PTE describes an area the size of the
753 * configured huge page size. This is twice the
754 * of the large TLB entry size we intend to use.
755 * A TLB entry half the size of the configured
756 * huge page size is configured into entrylo0
757 * and entrylo1 to cover the contiguous huge PTE
758 * address space.
759 */
760 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
761
762 /* We can clobber tmp. It isn't used after this.*/
763 if (!small_sequence)
764 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
765
766 build_convert_pte_to_entrylo(p, pte);
767 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
768 /* convert to entrylo1 */
769 if (small_sequence)
770 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
771 else
772 UASM_i_ADDU(p, pte, pte, tmp);
773
774 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
775 }
776
build_huge_handler_tail(u32 ** p,struct uasm_reloc ** r,struct uasm_label ** l,unsigned int pte,unsigned int ptr)777 static __cpuinit void build_huge_handler_tail(u32 **p,
778 struct uasm_reloc **r,
779 struct uasm_label **l,
780 unsigned int pte,
781 unsigned int ptr)
782 {
783 #ifdef CONFIG_SMP
784 UASM_i_SC(p, pte, 0, ptr);
785 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
786 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
787 #else
788 UASM_i_SW(p, pte, 0, ptr);
789 #endif
790 build_huge_update_entries(p, pte, ptr);
791 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
792 }
793 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
794
795 #ifdef CONFIG_64BIT
796 /*
797 * TMP and PTR are scratch.
798 * TMP will be clobbered, PTR will hold the pmd entry.
799 */
800 static void __cpuinit
build_get_pmde64(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,unsigned int ptr)801 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
802 unsigned int tmp, unsigned int ptr)
803 {
804 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
805 long pgdc = (long)pgd_current;
806 #endif
807 /*
808 * The vmalloc handling is not in the hotpath.
809 */
810 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
811
812 if (check_for_high_segbits) {
813 /*
814 * The kernel currently implicitely assumes that the
815 * MIPS SEGBITS parameter for the processor is
816 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
817 * allocate virtual addresses outside the maximum
818 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
819 * that doesn't prevent user code from accessing the
820 * higher xuseg addresses. Here, we make sure that
821 * everything but the lower xuseg addresses goes down
822 * the module_alloc/vmalloc path.
823 */
824 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
825 uasm_il_bnez(p, r, ptr, label_vmalloc);
826 } else {
827 uasm_il_bltz(p, r, tmp, label_vmalloc);
828 }
829 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
830
831 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
832 if (pgd_reg != -1) {
833 /* pgd is in pgd_reg */
834 UASM_i_MFC0(p, ptr, 31, pgd_reg);
835 } else {
836 /*
837 * &pgd << 11 stored in CONTEXT [23..63].
838 */
839 UASM_i_MFC0(p, ptr, C0_CONTEXT);
840
841 /* Clear lower 23 bits of context. */
842 uasm_i_dins(p, ptr, 0, 0, 23);
843
844 /* 1 0 1 0 1 << 6 xkphys cached */
845 uasm_i_ori(p, ptr, ptr, 0x540);
846 uasm_i_drotr(p, ptr, ptr, 11);
847 }
848 #elif defined(CONFIG_SMP)
849 # ifdef CONFIG_MIPS_MT_SMTC
850 /*
851 * SMTC uses TCBind value as "CPU" index
852 */
853 uasm_i_mfc0(p, ptr, C0_TCBIND);
854 uasm_i_dsrl_safe(p, ptr, ptr, 19);
855 # else
856 /*
857 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
858 * stored in CONTEXT.
859 */
860 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
861 uasm_i_dsrl_safe(p, ptr, ptr, 23);
862 # endif
863 UASM_i_LA_mostly(p, tmp, pgdc);
864 uasm_i_daddu(p, ptr, ptr, tmp);
865 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
866 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
867 #else
868 UASM_i_LA_mostly(p, ptr, pgdc);
869 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
870 #endif
871
872 uasm_l_vmalloc_done(l, *p);
873
874 /* get pgd offset in bytes */
875 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
876
877 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
878 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
879 #ifndef __PAGETABLE_PMD_FOLDED
880 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
881 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
882 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
883 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
884 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
885 #endif
886 }
887
888 /*
889 * BVADDR is the faulting address, PTR is scratch.
890 * PTR will hold the pgd for vmalloc.
891 */
892 static void __cpuinit
build_get_pgd_vmalloc64(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int bvaddr,unsigned int ptr,enum vmalloc64_mode mode)893 build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
894 unsigned int bvaddr, unsigned int ptr,
895 enum vmalloc64_mode mode)
896 {
897 long swpd = (long)swapper_pg_dir;
898 int single_insn_swpd;
899 int did_vmalloc_branch = 0;
900
901 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
902
903 uasm_l_vmalloc(l, *p);
904
905 if (mode != not_refill && check_for_high_segbits) {
906 if (single_insn_swpd) {
907 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
908 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
909 did_vmalloc_branch = 1;
910 /* fall through */
911 } else {
912 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
913 }
914 }
915 if (!did_vmalloc_branch) {
916 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
917 uasm_il_b(p, r, label_vmalloc_done);
918 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
919 } else {
920 UASM_i_LA_mostly(p, ptr, swpd);
921 uasm_il_b(p, r, label_vmalloc_done);
922 if (uasm_in_compat_space_p(swpd))
923 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
924 else
925 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
926 }
927 }
928 if (mode != not_refill && check_for_high_segbits) {
929 uasm_l_large_segbits_fault(l, *p);
930 /*
931 * We get here if we are an xsseg address, or if we are
932 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
933 *
934 * Ignoring xsseg (assume disabled so would generate
935 * (address errors?), the only remaining possibility
936 * is the upper xuseg addresses. On processors with
937 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
938 * addresses would have taken an address error. We try
939 * to mimic that here by taking a load/istream page
940 * fault.
941 */
942 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
943 uasm_i_jr(p, ptr);
944
945 if (mode == refill_scratch) {
946 if (scratch_reg > 0)
947 UASM_i_MFC0(p, 1, 31, scratch_reg);
948 else
949 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
950 } else {
951 uasm_i_nop(p);
952 }
953 }
954 }
955
956 #else /* !CONFIG_64BIT */
957
958 /*
959 * TMP and PTR are scratch.
960 * TMP will be clobbered, PTR will hold the pgd entry.
961 */
962 static void __cpuinit __maybe_unused
build_get_pgde32(u32 ** p,unsigned int tmp,unsigned int ptr)963 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
964 {
965 long pgdc = (long)pgd_current;
966
967 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
968 #ifdef CONFIG_SMP
969 #ifdef CONFIG_MIPS_MT_SMTC
970 /*
971 * SMTC uses TCBind value as "CPU" index
972 */
973 uasm_i_mfc0(p, ptr, C0_TCBIND);
974 UASM_i_LA_mostly(p, tmp, pgdc);
975 uasm_i_srl(p, ptr, ptr, 19);
976 #else
977 /*
978 * smp_processor_id() << 3 is stored in CONTEXT.
979 */
980 uasm_i_mfc0(p, ptr, C0_CONTEXT);
981 UASM_i_LA_mostly(p, tmp, pgdc);
982 uasm_i_srl(p, ptr, ptr, 23);
983 #endif
984 uasm_i_addu(p, ptr, tmp, ptr);
985 #else
986 UASM_i_LA_mostly(p, ptr, pgdc);
987 #endif
988 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
989 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
990
991 if (cpu_has_mips32r2 || cpu_has_mips32r6) {
992 uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT));
993 uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT));
994 return;
995 }
996
997 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
998 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
999 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1000
1001 }
1002
1003 #endif /* !CONFIG_64BIT */
1004
build_adjust_context(u32 ** p,unsigned int ctx)1005 static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
1006 {
1007 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1008 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1009
1010 switch (current_cpu_type()) {
1011 case CPU_VR41XX:
1012 case CPU_VR4111:
1013 case CPU_VR4121:
1014 case CPU_VR4122:
1015 case CPU_VR4131:
1016 case CPU_VR4181:
1017 case CPU_VR4181A:
1018 case CPU_VR4133:
1019 shift += 2;
1020 break;
1021
1022 default:
1023 break;
1024 }
1025
1026 if (shift)
1027 UASM_i_SRL(p, ctx, ctx, shift);
1028 uasm_i_andi(p, ctx, ctx, mask);
1029 }
1030
build_get_ptep(u32 ** p,unsigned int tmp,unsigned int ptr)1031 static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1032 {
1033 #ifndef CONFIG_64BIT
1034 if (cpu_has_mips_r2 || cpu_has_mips_r6) {
1035 /* For MIPS32R2, PTE ptr offset is obtained from BadVAddr */
1036 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1037 UASM_i_LW(p, ptr, 0, ptr);
1038 uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1);
1039 uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1);
1040 return;
1041 }
1042 #endif /* CONFIG_64BIT */
1043
1044 /*
1045 * Bug workaround for the Nevada. It seems as if under certain
1046 * circumstances the move from cp0_context might produce a
1047 * bogus result when the mfc0 instruction and its consumer are
1048 * in a different cacheline or a load instruction, probably any
1049 * memory reference, is between them.
1050 */
1051 switch (current_cpu_type()) {
1052 case CPU_NEVADA:
1053 UASM_i_LW(p, ptr, 0, ptr);
1054 GET_CONTEXT(p, tmp); /* get context reg */
1055 break;
1056
1057 default:
1058 GET_CONTEXT(p, tmp); /* get context reg */
1059 UASM_i_LW(p, ptr, 0, ptr);
1060 break;
1061 }
1062
1063 build_adjust_context(p, tmp);
1064 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1065 }
1066
build_update_entries(u32 ** p,unsigned int tmp,unsigned int ptep)1067 static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
1068 unsigned int ptep)
1069 {
1070 /*
1071 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1072 * Kernel is a special case. Only a few CPUs use it.
1073 */
1074 #ifdef CONFIG_64BIT_PHYS_ADDR
1075 if (cpu_has_64bits) {
1076 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
1077 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1078 if (cpu_has_rixi) {
1079 if (!cpu_has_himem) {
1080 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1081 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1082 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1083 } else {
1084 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
1085 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
1086 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1087 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1088 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1089 }
1090 } else {
1091 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1092 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1093 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1094 }
1095 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1096 } else {
1097 int pte_off_even = sizeof(pte_t) / 2;
1098 int pte_off_odd = pte_off_even + sizeof(pte_t);
1099
1100 /* The pte entries are pre-shifted */
1101 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1102 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1103 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1104 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1105 }
1106 #else
1107 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
1108 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1109 if (r45k_bvahwbug())
1110 build_tlb_probe_entry(p);
1111 if (cpu_has_rixi) {
1112 if (!cpu_has_himem)
1113 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1114 else {
1115 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
1116 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
1117 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1118 }
1119 if (r4k_250MHZhwbug())
1120 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1121 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1122 if (!cpu_has_himem)
1123 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL));
1124 else
1125 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
1126 } else {
1127 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
1128 if (r4k_250MHZhwbug())
1129 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1130 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1131 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
1132 if (r45k_bvahwbug())
1133 uasm_i_mfc0(p, tmp, C0_INDEX);
1134 }
1135 if (r4k_250MHZhwbug())
1136 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1137 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1138 #endif
1139 }
1140
1141 struct mips_huge_tlb_info {
1142 int huge_pte;
1143 int restore_scratch;
1144 };
1145
1146 static struct mips_huge_tlb_info __cpuinit
build_fast_tlb_refill_handler(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,unsigned int ptr,int c0_scratch)1147 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1148 struct uasm_reloc **r, unsigned int tmp,
1149 unsigned int ptr, int c0_scratch)
1150 {
1151 struct mips_huge_tlb_info rv;
1152 unsigned int even, odd;
1153 int vmalloc_branch_delay_filled = 0;
1154 const int scratch = 1; /* Our extra working register */
1155
1156 rv.huge_pte = scratch;
1157 rv.restore_scratch = 0;
1158
1159 if (check_for_high_segbits) {
1160 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1161
1162 if (pgd_reg != -1)
1163 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1164 else
1165 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1166
1167 if (c0_scratch >= 0)
1168 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1169 else
1170 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1171
1172 uasm_i_dsrl_safe(p, scratch, tmp,
1173 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1174 uasm_il_bnez(p, r, scratch, label_vmalloc);
1175
1176 if (pgd_reg == -1) {
1177 vmalloc_branch_delay_filled = 1;
1178 /* Clear lower 23 bits of context. */
1179 uasm_i_dins(p, ptr, 0, 0, 23);
1180 }
1181 } else {
1182 if (pgd_reg != -1)
1183 UASM_i_MFC0(p, ptr, 31, pgd_reg);
1184 else
1185 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1186
1187 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1188
1189 if (c0_scratch >= 0)
1190 UASM_i_MTC0(p, scratch, 31, c0_scratch);
1191 else
1192 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1193
1194 if (pgd_reg == -1)
1195 /* Clear lower 23 bits of context. */
1196 uasm_i_dins(p, ptr, 0, 0, 23);
1197
1198 uasm_il_bltz(p, r, tmp, label_vmalloc);
1199 }
1200
1201 if (pgd_reg == -1) {
1202 vmalloc_branch_delay_filled = 1;
1203 /* 1 0 1 0 1 << 6 xkphys cached */
1204 uasm_i_ori(p, ptr, ptr, 0x540);
1205 uasm_i_drotr(p, ptr, ptr, 11);
1206 }
1207
1208 #ifdef __PAGETABLE_PMD_FOLDED
1209 #define LOC_PTEP scratch
1210 #else
1211 #define LOC_PTEP ptr
1212 #endif
1213
1214 if (!vmalloc_branch_delay_filled)
1215 /* get pgd offset in bytes */
1216 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1217
1218 uasm_l_vmalloc_done(l, *p);
1219
1220 /*
1221 * tmp ptr
1222 * fall-through case = badvaddr *pgd_current
1223 * vmalloc case = badvaddr swapper_pg_dir
1224 */
1225
1226 if (vmalloc_branch_delay_filled)
1227 /* get pgd offset in bytes */
1228 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1229
1230 #ifdef __PAGETABLE_PMD_FOLDED
1231 GET_CONTEXT(p, tmp); /* get context reg */
1232 #endif
1233 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1234
1235 if (use_lwx_insns()) {
1236 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1237 } else {
1238 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1239 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1240 }
1241
1242 #ifndef __PAGETABLE_PMD_FOLDED
1243 /* get pmd offset in bytes */
1244 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1245 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1246 GET_CONTEXT(p, tmp); /* get context reg */
1247
1248 if (use_lwx_insns()) {
1249 UASM_i_LWX(p, scratch, scratch, ptr);
1250 } else {
1251 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1252 UASM_i_LW(p, scratch, 0, ptr);
1253 }
1254 #endif
1255 /* Adjust the context during the load latency. */
1256 build_adjust_context(p, tmp);
1257
1258 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1259 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1260 /*
1261 * The in the LWX case we don't want to do the load in the
1262 * delay slot. It cannot issue in the same cycle and may be
1263 * speculative and unneeded.
1264 */
1265 if (use_lwx_insns())
1266 uasm_i_nop(p);
1267 #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
1268
1269
1270 /* build_update_entries */
1271 if (use_lwx_insns()) {
1272 even = ptr;
1273 odd = tmp;
1274 UASM_i_LWX(p, even, scratch, tmp);
1275 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1276 UASM_i_LWX(p, odd, scratch, tmp);
1277 } else {
1278 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1279 even = tmp;
1280 odd = ptr;
1281 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1282 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1283 }
1284 if (cpu_has_rixi) {
1285 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
1286 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1287 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
1288 } else {
1289 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1290 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1291 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1292 }
1293 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1294
1295 if (c0_scratch >= 0) {
1296 UASM_i_MFC0(p, scratch, 31, c0_scratch);
1297 build_tlb_write_entry(p, l, r, tlb_random);
1298 uasm_l_leave(l, *p);
1299 rv.restore_scratch = 1;
1300 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1301 build_tlb_write_entry(p, l, r, tlb_random);
1302 uasm_l_leave(l, *p);
1303 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1304 } else {
1305 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1306 build_tlb_write_entry(p, l, r, tlb_random);
1307 uasm_l_leave(l, *p);
1308 rv.restore_scratch = 1;
1309 }
1310
1311 uasm_i_eret(p); /* return from trap */
1312
1313 return rv;
1314 }
1315
1316 /*
1317 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1318 * because EXL == 0. If we wrap, we can also use the 32 instruction
1319 * slots before the XTLB refill exception handler which belong to the
1320 * unused TLB refill exception.
1321 */
1322 #define MIPS64_REFILL_INSNS 32
1323
build_r4000_tlb_refill_handler(void)1324 static void __cpuinit build_r4000_tlb_refill_handler(void)
1325 {
1326 u32 *p = tlb_handler;
1327 struct uasm_label *l = labels;
1328 struct uasm_reloc *r = relocs;
1329 u32 *f;
1330 unsigned int final_len;
1331 struct mips_huge_tlb_info htlb_info __maybe_unused;
1332 enum vmalloc64_mode vmalloc_mode __maybe_unused;
1333
1334 memset(tlb_handler, 0, sizeof(tlb_handler));
1335 memset(labels, 0, sizeof(labels));
1336 memset(relocs, 0, sizeof(relocs));
1337 memset(final_handler, 0, sizeof(final_handler));
1338
1339 if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) {
1340 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1341 scratch_reg);
1342 vmalloc_mode = refill_scratch;
1343 } else {
1344 htlb_info.huge_pte = K0;
1345 htlb_info.restore_scratch = 0;
1346 vmalloc_mode = refill_noscratch;
1347 /*
1348 * create the plain linear handler
1349 */
1350 if (bcm1250_m3_war()) {
1351 unsigned int segbits = 44;
1352
1353 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1354 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1355 uasm_i_xor(&p, K0, K0, K1);
1356 uasm_i_dsrl_safe(&p, K1, K0, 62);
1357 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1358 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1359 uasm_i_or(&p, K0, K0, K1);
1360 uasm_il_bnez(&p, &r, K0, label_leave);
1361 /* No need for uasm_i_nop */
1362 }
1363
1364 #ifdef CONFIG_64BIT
1365 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1366 #else
1367 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1368 #endif
1369
1370 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1371 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
1372 #endif
1373
1374 build_get_ptep(&p, K0, K1);
1375 build_update_entries(&p, K0, K1);
1376 build_tlb_write_entry(&p, &l, &r, tlb_random);
1377 uasm_l_leave(&l, p);
1378 uasm_i_eret(&p); /* return from trap */
1379 }
1380 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1381 uasm_l_tlb_huge_update(&l, p);
1382 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1383 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1384 htlb_info.restore_scratch);
1385 #endif
1386
1387 #ifdef CONFIG_64BIT
1388 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1389 #endif
1390
1391 /*
1392 * Overflow check: For the 64bit handler, we need at least one
1393 * free instruction slot for the wrap-around branch. In worst
1394 * case, if the intended insertion point is a delay slot, we
1395 * need three, with the second nop'ed and the third being
1396 * unused.
1397 */
1398 /* Loongson2 ebase is different than r4k, we have more space */
1399 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1400 if ((p - tlb_handler) > 64)
1401 panic("TLB refill handler space exceeded");
1402 #else
1403 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1404 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1405 && uasm_insn_has_bdelay(relocs,
1406 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1407 panic("TLB refill handler space exceeded");
1408 #endif
1409
1410 /*
1411 * Now fold the handler in the TLB refill handler space.
1412 */
1413 #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
1414 f = final_handler;
1415 /* Simplest case, just copy the handler. */
1416 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1417 final_len = p - tlb_handler;
1418 #else /* CONFIG_64BIT */
1419 f = final_handler + MIPS64_REFILL_INSNS;
1420 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1421 /* Just copy the handler. */
1422 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1423 final_len = p - tlb_handler;
1424 } else {
1425 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1426 const enum label_id ls = label_tlb_huge_update;
1427 #else
1428 const enum label_id ls = label_vmalloc;
1429 #endif
1430 u32 *split;
1431 int ov = 0;
1432 int i;
1433
1434 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1435 ;
1436 BUG_ON(i == ARRAY_SIZE(labels));
1437 split = labels[i].addr;
1438
1439 /*
1440 * See if we have overflown one way or the other.
1441 */
1442 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1443 split < p - MIPS64_REFILL_INSNS)
1444 ov = 1;
1445
1446 if (ov) {
1447 /*
1448 * Split two instructions before the end. One
1449 * for the branch and one for the instruction
1450 * in the delay slot.
1451 */
1452 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1453
1454 /*
1455 * If the branch would fall in a delay slot,
1456 * we must back up an additional instruction
1457 * so that it is no longer in a delay slot.
1458 */
1459 if (uasm_insn_has_bdelay(relocs, split - 1))
1460 split--;
1461 }
1462 /* Copy first part of the handler. */
1463 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1464 f += split - tlb_handler;
1465
1466 if (ov) {
1467 /* Insert branch. */
1468 uasm_l_split(&l, final_handler);
1469 uasm_il_b(&f, &r, label_split);
1470 if (uasm_insn_has_bdelay(relocs, split))
1471 uasm_i_nop(&f);
1472 else {
1473 uasm_copy_handler(relocs, labels,
1474 split, split + 1, f);
1475 uasm_move_labels(labels, f, f + 1, -1);
1476 f++;
1477 split++;
1478 }
1479 }
1480
1481 /* Copy the rest of the handler. */
1482 uasm_copy_handler(relocs, labels, split, p, final_handler);
1483 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1484 (p - split);
1485 }
1486 #endif /* CONFIG_64BIT */
1487
1488 uasm_resolve_relocs(relocs, labels);
1489 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1490 final_len);
1491
1492 memcpy((void *)ebase, final_handler, 0x100);
1493 local_flush_icache_range(ebase, ebase + 0x100);
1494
1495 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1496 }
1497
1498 /*
1499 * 128 instructions for the fastpath handler is generous and should
1500 * never be exceeded.
1501 */
1502 #define FASTPATH_SIZE 128
1503
1504 u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
1505 u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
1506 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
1507 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
1508 u32 tlbmiss_handler_setup_pgd_array[16] __cacheline_aligned;
1509
build_r4000_setup_pgd(void)1510 static void __cpuinit build_r4000_setup_pgd(void)
1511 {
1512 const int a0 = 4;
1513 const int a1 = 5;
1514 u32 *p = tlbmiss_handler_setup_pgd_array;
1515 struct uasm_label *l = labels;
1516 struct uasm_reloc *r = relocs;
1517
1518 memset(tlbmiss_handler_setup_pgd_array, 0, sizeof(tlbmiss_handler_setup_pgd_array));
1519 memset(labels, 0, sizeof(labels));
1520 memset(relocs, 0, sizeof(relocs));
1521
1522 pgd_reg = allocate_kscratch();
1523
1524 if (pgd_reg == -1) {
1525 /* PGD << 11 in c0_Context */
1526 /*
1527 * If it is a ckseg0 address, convert to a physical
1528 * address. Shifting right by 29 and adding 4 will
1529 * result in zero for these addresses.
1530 *
1531 */
1532 UASM_i_SRA(&p, a1, a0, 29);
1533 UASM_i_ADDIU(&p, a1, a1, 4);
1534 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1535 uasm_i_nop(&p);
1536 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1537 uasm_l_tlbl_goaround1(&l, p);
1538 UASM_i_SLL(&p, a0, a0, 11);
1539 uasm_i_jr(&p, 31);
1540 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1541 } else {
1542 /* PGD in c0_KScratch */
1543 uasm_i_jr(&p, 31);
1544 UASM_i_MTC0(&p, a0, 31, pgd_reg);
1545 }
1546 if (p - tlbmiss_handler_setup_pgd_array > ARRAY_SIZE(tlbmiss_handler_setup_pgd_array))
1547 panic("tlbmiss_handler_setup_pgd_array space exceeded");
1548 uasm_resolve_relocs(relocs, labels);
1549 pr_debug("Wrote tlbmiss_handler_setup_pgd_array (%u instructions).\n",
1550 (unsigned int)(p - tlbmiss_handler_setup_pgd_array));
1551
1552 dump_handler("tlbmiss_handler",
1553 tlbmiss_handler_setup_pgd_array,
1554 ARRAY_SIZE(tlbmiss_handler_setup_pgd_array));
1555 }
1556 #endif
1557
1558 static void __cpuinit
iPTE_LW(u32 ** p,unsigned int pte,unsigned int ptr)1559 iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1560 {
1561 #ifdef CONFIG_SMP
1562 # ifdef CONFIG_64BIT_PHYS_ADDR
1563 if (cpu_has_64bits)
1564 uasm_i_lld(p, pte, 0, ptr);
1565 else
1566 # endif
1567 UASM_i_LL(p, pte, 0, ptr);
1568 #else
1569 # ifdef CONFIG_64BIT_PHYS_ADDR
1570 if (cpu_has_64bits)
1571 uasm_i_ld(p, pte, 0, ptr);
1572 else
1573 # endif
1574 UASM_i_LW(p, pte, 0, ptr);
1575 #endif
1576 }
1577
1578 static void __cpuinit
iPTE_SW(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,unsigned int mode)1579 iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
1580 unsigned int mode)
1581 {
1582 #ifdef CONFIG_64BIT_PHYS_ADDR
1583 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1584 #endif
1585
1586 uasm_i_ori(p, pte, pte, mode);
1587 #ifdef CONFIG_SMP
1588 # ifdef CONFIG_64BIT_PHYS_ADDR
1589 if (cpu_has_64bits)
1590 uasm_i_scd(p, pte, 0, ptr);
1591 else
1592 # endif
1593 UASM_i_SC(p, pte, 0, ptr);
1594
1595 if (r10000_llsc_war())
1596 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1597 else
1598 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1599
1600 # ifdef CONFIG_64BIT_PHYS_ADDR
1601 if (!cpu_has_64bits) {
1602 /* no uasm_i_nop needed */
1603 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1604 uasm_i_ori(p, pte, pte, hwmode);
1605 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1606 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1607 /* no uasm_i_nop needed */
1608 uasm_i_lw(p, pte, 0, ptr);
1609 } else
1610 uasm_i_nop(p);
1611 # else
1612 uasm_i_nop(p);
1613 # endif
1614 #else
1615 # ifdef CONFIG_64BIT_PHYS_ADDR
1616 if (cpu_has_64bits)
1617 uasm_i_sd(p, pte, 0, ptr);
1618 else
1619 # endif
1620 UASM_i_SW(p, pte, 0, ptr);
1621
1622 # ifdef CONFIG_64BIT_PHYS_ADDR
1623 if (!cpu_has_64bits) {
1624 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1625 uasm_i_ori(p, pte, pte, hwmode);
1626 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1627 uasm_i_lw(p, pte, 0, ptr);
1628 }
1629 # endif
1630 #endif
1631 }
1632
1633 /*
1634 * Check if PTE is present, if not then jump to LABEL. PTR points to
1635 * the page table where this PTE is located, PTE will be re-loaded
1636 * with it's original value.
1637 */
1638 static void __cpuinit
build_pte_present(u32 ** p,struct uasm_reloc ** r,int pte,int ptr,int scratch,enum label_id lid)1639 build_pte_present(u32 **p, struct uasm_reloc **r,
1640 int pte, int ptr, int scratch, enum label_id lid)
1641 {
1642 int t = scratch >= 0 ? scratch : pte;
1643
1644 if (cpu_has_rixi) {
1645 if (use_bbit_insns()) {
1646 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1647 uasm_i_nop(p);
1648 } else {
1649 uasm_i_andi(p, t, pte, _PAGE_PRESENT);
1650 uasm_il_beqz(p, r, t, lid);
1651 if (pte == t)
1652 /* You lose the SMP race :-(*/
1653 iPTE_LW(p, pte, ptr);
1654 }
1655 } else {
1656 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ);
1657 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ);
1658 uasm_il_bnez(p, r, t, lid);
1659 if (pte == t)
1660 /* You lose the SMP race :-(*/
1661 iPTE_LW(p, pte, ptr);
1662 }
1663 }
1664
1665 /* Make PTE valid, store result in PTR. */
1666 static void __cpuinit
build_make_valid(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr)1667 build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
1668 unsigned int ptr)
1669 {
1670 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1671
1672 iPTE_SW(p, r, pte, ptr, mode);
1673 }
1674
1675 /*
1676 * Check if PTE can be written to, if not branch to LABEL. Regardless
1677 * restore PTE with value from PTR when done.
1678 */
1679 static void __cpuinit
build_pte_writable(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,int scratch,enum label_id lid)1680 build_pte_writable(u32 **p, struct uasm_reloc **r,
1681 unsigned int pte, unsigned int ptr, int scratch,
1682 enum label_id lid)
1683 {
1684 int t = scratch >= 0 ? scratch : pte;
1685
1686 uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE);
1687 uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE);
1688 uasm_il_bnez(p, r, t, lid);
1689 if (pte == t)
1690 /* You lose the SMP race :-(*/
1691 iPTE_LW(p, pte, ptr);
1692 else
1693 uasm_i_nop(p);
1694 }
1695
1696 /* Make PTE writable, update software status bits as well, then store
1697 * at PTR.
1698 */
1699 static void __cpuinit
build_make_write(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr)1700 build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
1701 unsigned int ptr)
1702 {
1703 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1704 | _PAGE_DIRTY);
1705
1706 iPTE_SW(p, r, pte, ptr, mode);
1707 }
1708
1709 /*
1710 * Check if PTE can be modified, if not branch to LABEL. Regardless
1711 * restore PTE with value from PTR when done.
1712 */
1713 static void __cpuinit
build_pte_modifiable(u32 ** p,struct uasm_reloc ** r,unsigned int pte,unsigned int ptr,int scratch,enum label_id lid)1714 build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1715 unsigned int pte, unsigned int ptr, int scratch,
1716 enum label_id lid)
1717 {
1718 if (use_bbit_insns()) {
1719 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1720 uasm_i_nop(p);
1721 } else {
1722 int t = scratch >= 0 ? scratch : pte;
1723 uasm_i_andi(p, t, pte, _PAGE_WRITE);
1724 uasm_il_beqz(p, r, t, lid);
1725 if (pte == t)
1726 /* You lose the SMP race :-(*/
1727 iPTE_LW(p, pte, ptr);
1728 }
1729 }
1730
1731 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1732
1733
1734 /*
1735 * R3000 style TLB load/store/modify handlers.
1736 */
1737
1738 /*
1739 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1740 * Then it returns.
1741 */
1742 static void __cpuinit
build_r3000_pte_reload_tlbwi(u32 ** p,unsigned int pte,unsigned int tmp)1743 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1744 {
1745 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1746 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1747 uasm_i_tlbwi(p);
1748 uasm_i_jr(p, tmp);
1749 uasm_i_rfe(p); /* branch delay */
1750 }
1751
1752 /*
1753 * This places the pte into ENTRYLO0 and writes it with tlbwi
1754 * or tlbwr as appropriate. This is because the index register
1755 * may have the probe fail bit set as a result of a trap on a
1756 * kseg2 access, i.e. without refill. Then it returns.
1757 */
1758 static void __cpuinit
build_r3000_tlb_reload_write(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int pte,unsigned int tmp)1759 build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1760 struct uasm_reloc **r, unsigned int pte,
1761 unsigned int tmp)
1762 {
1763 uasm_i_mfc0(p, tmp, C0_INDEX);
1764 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1765 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1766 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1767 uasm_i_tlbwi(p); /* cp0 delay */
1768 uasm_i_jr(p, tmp);
1769 uasm_i_rfe(p); /* branch delay */
1770 uasm_l_r3000_write_probe_fail(l, *p);
1771 uasm_i_tlbwr(p); /* cp0 delay */
1772 uasm_i_jr(p, tmp);
1773 uasm_i_rfe(p); /* branch delay */
1774 }
1775
1776 static void __cpuinit
build_r3000_tlbchange_handler_head(u32 ** p,unsigned int pte,unsigned int ptr)1777 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1778 unsigned int ptr)
1779 {
1780 long pgdc = (long)pgd_current;
1781
1782 uasm_i_mfc0(p, pte, C0_BADVADDR);
1783 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1784 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1785 uasm_i_srl(p, pte, pte, 22); /* load delay */
1786 uasm_i_sll(p, pte, pte, 2);
1787 uasm_i_addu(p, ptr, ptr, pte);
1788 uasm_i_mfc0(p, pte, C0_CONTEXT);
1789 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1790 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1791 uasm_i_addu(p, ptr, ptr, pte);
1792 uasm_i_lw(p, pte, 0, ptr);
1793 uasm_i_tlbp(p); /* load delay */
1794 }
1795
build_r3000_tlb_load_handler(void)1796 static void __cpuinit build_r3000_tlb_load_handler(void)
1797 {
1798 u32 *p = handle_tlbl;
1799 struct uasm_label *l = labels;
1800 struct uasm_reloc *r = relocs;
1801
1802 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1803 memset(labels, 0, sizeof(labels));
1804 memset(relocs, 0, sizeof(relocs));
1805
1806 build_r3000_tlbchange_handler_head(&p, K0, K1);
1807 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
1808 uasm_i_nop(&p); /* load delay */
1809 build_make_valid(&p, &r, K0, K1);
1810 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1811
1812 uasm_l_nopage_tlbl(&l, p);
1813 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1814 uasm_i_nop(&p);
1815
1816 if ((p - handle_tlbl) > FASTPATH_SIZE)
1817 panic("TLB load handler fastpath space exceeded");
1818
1819 uasm_resolve_relocs(relocs, labels);
1820 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1821 (unsigned int)(p - handle_tlbl));
1822
1823 dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
1824 }
1825
build_r3000_tlb_store_handler(void)1826 static void __cpuinit build_r3000_tlb_store_handler(void)
1827 {
1828 u32 *p = handle_tlbs;
1829 struct uasm_label *l = labels;
1830 struct uasm_reloc *r = relocs;
1831
1832 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1833 memset(labels, 0, sizeof(labels));
1834 memset(relocs, 0, sizeof(relocs));
1835
1836 build_r3000_tlbchange_handler_head(&p, K0, K1);
1837 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
1838 uasm_i_nop(&p); /* load delay */
1839 build_make_write(&p, &r, K0, K1);
1840 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1841
1842 uasm_l_nopage_tlbs(&l, p);
1843 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1844 uasm_i_nop(&p);
1845
1846 if ((p - handle_tlbs) > FASTPATH_SIZE)
1847 panic("TLB store handler fastpath space exceeded");
1848
1849 uasm_resolve_relocs(relocs, labels);
1850 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1851 (unsigned int)(p - handle_tlbs));
1852
1853 dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
1854 }
1855
build_r3000_tlb_modify_handler(void)1856 static void __cpuinit build_r3000_tlb_modify_handler(void)
1857 {
1858 u32 *p = handle_tlbm;
1859 struct uasm_label *l = labels;
1860 struct uasm_reloc *r = relocs;
1861
1862 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1863 memset(labels, 0, sizeof(labels));
1864 memset(relocs, 0, sizeof(relocs));
1865
1866 build_r3000_tlbchange_handler_head(&p, K0, K1);
1867 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
1868 uasm_i_nop(&p); /* load delay */
1869 build_make_write(&p, &r, K0, K1);
1870 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1871
1872 uasm_l_nopage_tlbm(&l, p);
1873 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1874 uasm_i_nop(&p);
1875
1876 if ((p - handle_tlbm) > FASTPATH_SIZE)
1877 panic("TLB modify handler fastpath space exceeded");
1878
1879 uasm_resolve_relocs(relocs, labels);
1880 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1881 (unsigned int)(p - handle_tlbm));
1882
1883 dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
1884 }
1885 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1886
1887 /*
1888 * R4000 style TLB load/store/modify handlers.
1889 */
1890 static struct work_registers __cpuinit
build_r4000_tlbchange_handler_head(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r)1891 build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1892 struct uasm_reloc **r)
1893 {
1894 struct work_registers wr = build_get_work_registers(p);
1895
1896 #ifdef CONFIG_64BIT
1897 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1898 #else
1899 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1900 #endif
1901
1902 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1903 /*
1904 * For huge tlb entries, pmd doesn't contain an address but
1905 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1906 * see if we need to jump to huge tlb processing.
1907 */
1908 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
1909 #endif
1910
1911 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
1912 UASM_i_LW(p, wr.r2, 0, wr.r2);
1913 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1914 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1915 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1916
1917 #ifdef CONFIG_SMP
1918 uasm_l_smp_pgtable_change(l, *p);
1919 #endif
1920 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
1921 if (!m4kc_tlbp_war()) {
1922 build_tlb_probe_entry(p);
1923 if (cpu_has_htw) {
1924 /* race condition happens, leaving */
1925 uasm_i_ehb(p);
1926 uasm_i_mfc0(p, wr.r3, C0_INDEX);
1927 uasm_il_bltz(p, r, wr.r3, label_leave);
1928 uasm_i_nop(p);
1929 }
1930 }
1931 return wr;
1932 }
1933
1934 static void __cpuinit
build_r4000_tlbchange_handler_tail(u32 ** p,struct uasm_label ** l,struct uasm_reloc ** r,unsigned int tmp,unsigned int ptr)1935 build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1936 struct uasm_reloc **r, unsigned int tmp,
1937 unsigned int ptr)
1938 {
1939 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1940 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1941 build_update_entries(p, tmp, ptr);
1942 build_tlb_write_entry(p, l, r, tlb_indexed);
1943 uasm_l_leave(l, *p);
1944 build_restore_work_registers(p);
1945 uasm_i_eret(p); /* return from trap */
1946
1947 #ifdef CONFIG_64BIT
1948 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1949 #endif
1950 }
1951
build_r4000_tlb_load_handler(void)1952 static void __cpuinit build_r4000_tlb_load_handler(void)
1953 {
1954 u32 *p = handle_tlbl;
1955 struct uasm_label *l = labels;
1956 struct uasm_reloc *r = relocs;
1957 struct work_registers wr;
1958
1959 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1960 memset(labels, 0, sizeof(labels));
1961 memset(relocs, 0, sizeof(relocs));
1962
1963 if (bcm1250_m3_war()) {
1964 unsigned int segbits = 44;
1965
1966 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1967 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1968 uasm_i_xor(&p, K0, K0, K1);
1969 uasm_i_dsrl_safe(&p, K1, K0, 62);
1970 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1971 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1972 uasm_i_or(&p, K0, K0, K1);
1973 uasm_il_bnez(&p, &r, K0, label_leave);
1974 /* No need for uasm_i_nop */
1975 }
1976
1977 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
1978 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
1979 if (m4kc_tlbp_war())
1980 build_tlb_probe_entry(&p);
1981
1982 if (cpu_has_rixi && !cpu_has_rixi_except) {
1983 /*
1984 * If the page is not _PAGE_VALID, RI or XI could not
1985 * have triggered it. Skip the expensive test..
1986 */
1987 if (use_bbit_insns()) {
1988 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
1989 label_tlbl_goaround1);
1990 } else {
1991 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
1992 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
1993 }
1994 uasm_i_nop(&p);
1995
1996 uasm_i_tlbr(&p);
1997
1998 switch (current_cpu_type()) {
1999 default:
2000 if (cpu_has_mips_r2 || cpu_has_mips_r6) {
2001 uasm_i_ehb(&p);
2002
2003 case CPU_CAVIUM_OCTEON:
2004 case CPU_CAVIUM_OCTEON_PLUS:
2005 case CPU_CAVIUM_OCTEON2:
2006 break;
2007 }
2008 }
2009
2010 /* Examine entrylo 0 or 1 based on ptr. */
2011 if (use_bbit_insns()) {
2012 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2013 } else {
2014 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2015 uasm_i_beqz(&p, wr.r3, 8);
2016 }
2017 /* load it in the delay slot*/
2018 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2019 /* load it if ptr is odd */
2020 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2021 /*
2022 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2023 * XI must have triggered it.
2024 */
2025 if (use_bbit_insns()) {
2026 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2027 uasm_i_nop(&p);
2028 uasm_l_tlbl_goaround1(&l, p);
2029 } else {
2030 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2031 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2032 uasm_i_nop(&p);
2033 }
2034 uasm_l_tlbl_goaround1(&l, p);
2035 }
2036 build_make_valid(&p, &r, wr.r1, wr.r2);
2037 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2038
2039 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2040 /*
2041 * This is the entry point when build_r4000_tlbchange_handler_head
2042 * spots a huge page.
2043 */
2044 uasm_l_tlb_huge_update(&l, p);
2045 iPTE_LW(&p, wr.r1, wr.r2);
2046 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
2047 build_tlb_probe_entry(&p);
2048
2049 if (cpu_has_rixi && !cpu_has_rixi_except) {
2050 /*
2051 * If the page is not _PAGE_VALID, RI or XI could not
2052 * have triggered it. Skip the expensive test..
2053 */
2054 if (use_bbit_insns()) {
2055 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
2056 label_tlbl_goaround2);
2057 } else {
2058 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2059 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2060 }
2061 uasm_i_nop(&p);
2062
2063 uasm_i_tlbr(&p);
2064
2065 switch (current_cpu_type()) {
2066 default:
2067 if (cpu_has_mips_r2 || cpu_has_mips_r6) {
2068 uasm_i_ehb(&p);
2069
2070 case CPU_CAVIUM_OCTEON:
2071 case CPU_CAVIUM_OCTEON_PLUS:
2072 case CPU_CAVIUM_OCTEON2:
2073 break;
2074 }
2075 }
2076
2077 /* Examine entrylo 0 or 1 based on ptr. */
2078 if (use_bbit_insns()) {
2079 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
2080 } else {
2081 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2082 uasm_i_beqz(&p, wr.r3, 8);
2083 }
2084 /* load it in the delay slot*/
2085 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2086 /* load it if ptr is odd */
2087 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
2088 /*
2089 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
2090 * XI must have triggered it.
2091 */
2092 if (use_bbit_insns()) {
2093 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
2094 } else {
2095 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2096 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
2097 }
2098 if (PM_DEFAULT_MASK == 0)
2099 uasm_i_nop(&p);
2100 /*
2101 * We clobbered C0_PAGEMASK, restore it. On the other branch
2102 * it is restored in build_huge_tlb_write_entry.
2103 */
2104 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
2105
2106 uasm_l_tlbl_goaround2(&l, p);
2107 }
2108 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
2109 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2110 #endif
2111
2112 uasm_l_nopage_tlbl(&l, p);
2113 build_restore_work_registers(&p);
2114 #ifdef CONFIG_CPU_MICROMIPS
2115 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2116 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2117 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2118 uasm_i_jr(&p, K0);
2119 } else
2120 #endif
2121 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2122 uasm_i_nop(&p);
2123
2124 if ((p - handle_tlbl) > FASTPATH_SIZE)
2125 panic("TLB load handler fastpath space exceeded");
2126
2127 uasm_resolve_relocs(relocs, labels);
2128 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2129 (unsigned int)(p - handle_tlbl));
2130
2131 dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl));
2132 }
2133
build_r4000_tlb_store_handler(void)2134 static void __cpuinit build_r4000_tlb_store_handler(void)
2135 {
2136 u32 *p = handle_tlbs;
2137 struct uasm_label *l = labels;
2138 struct uasm_reloc *r = relocs;
2139 struct work_registers wr;
2140
2141 memset(handle_tlbs, 0, sizeof(handle_tlbs));
2142 memset(labels, 0, sizeof(labels));
2143 memset(relocs, 0, sizeof(relocs));
2144
2145 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2146 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2147 if (m4kc_tlbp_war())
2148 build_tlb_probe_entry(&p);
2149 build_make_write(&p, &r, wr.r1, wr.r2);
2150 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2151
2152 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2153 /*
2154 * This is the entry point when
2155 * build_r4000_tlbchange_handler_head spots a huge page.
2156 */
2157 uasm_l_tlb_huge_update(&l, p);
2158 iPTE_LW(&p, wr.r1, wr.r2);
2159 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
2160 build_tlb_probe_entry(&p);
2161 uasm_i_ori(&p, wr.r1, wr.r1,
2162 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2163 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2164 #endif
2165
2166 uasm_l_nopage_tlbs(&l, p);
2167 build_restore_work_registers(&p);
2168 #ifdef CONFIG_CPU_MICROMIPS
2169 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2170 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2171 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2172 uasm_i_jr(&p, K0);
2173 } else
2174 #endif
2175 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2176 uasm_i_nop(&p);
2177
2178 if ((p - handle_tlbs) > FASTPATH_SIZE)
2179 panic("TLB store handler fastpath space exceeded");
2180
2181 uasm_resolve_relocs(relocs, labels);
2182 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2183 (unsigned int)(p - handle_tlbs));
2184
2185 dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs));
2186 }
2187
build_r4000_tlb_modify_handler(void)2188 static void __cpuinit build_r4000_tlb_modify_handler(void)
2189 {
2190 u32 *p = handle_tlbm;
2191 struct uasm_label *l = labels;
2192 struct uasm_reloc *r = relocs;
2193 struct work_registers wr;
2194
2195 memset(handle_tlbm, 0, sizeof(handle_tlbm));
2196 memset(labels, 0, sizeof(labels));
2197 memset(relocs, 0, sizeof(relocs));
2198
2199 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2200 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2201 if (m4kc_tlbp_war())
2202 build_tlb_probe_entry(&p);
2203 /* Present and writable bits set, set accessed and dirty bits. */
2204 build_make_write(&p, &r, wr.r1, wr.r2);
2205 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
2206
2207 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2208 /*
2209 * This is the entry point when
2210 * build_r4000_tlbchange_handler_head spots a huge page.
2211 */
2212 uasm_l_tlb_huge_update(&l, p);
2213 iPTE_LW(&p, wr.r1, wr.r2);
2214 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
2215 build_tlb_probe_entry(&p);
2216 uasm_i_ori(&p, wr.r1, wr.r1,
2217 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
2218 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2);
2219 #endif
2220
2221 uasm_l_nopage_tlbm(&l, p);
2222 build_restore_work_registers(&p);
2223 #ifdef CONFIG_CPU_MICROMIPS
2224 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2225 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2226 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2227 uasm_i_jr(&p, K0);
2228 } else
2229 #endif
2230 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2231 uasm_i_nop(&p);
2232
2233 if ((p - handle_tlbm) > FASTPATH_SIZE)
2234 panic("TLB modify handler fastpath space exceeded");
2235
2236 uasm_resolve_relocs(relocs, labels);
2237 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2238 (unsigned int)(p - handle_tlbm));
2239
2240 dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm));
2241 }
2242
print_htw_config(void)2243 static void print_htw_config(void)
2244 {
2245 unsigned long config;
2246 unsigned int pwctl;
2247 const int field = 2 * sizeof(unsigned long);
2248
2249 config = read_c0_pwfield();
2250 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2251 field, config,
2252 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2253 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2254 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2255 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2256 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2257
2258 config = read_c0_pwsize();
2259 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
2260 field, config,
2261 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2262 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2263 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2264 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2265 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2266
2267 pwctl = read_c0_pwctl();
2268 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
2269 pwctl,
2270 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
2271 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2272 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2273 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2274 }
2275
config_htw_params(void)2276 static void config_htw_params(void)
2277 {
2278 unsigned long pwfield, pwsize, ptei;
2279
2280 /*
2281 * We are using 2-level page tables, so we only need to
2282 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2283 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2284 * write values less than 0xc in these fields because the entire
2285 * write will be dropped. As a result of which, we must preserve
2286 * the original reset values and overwrite only what we really want.
2287 */
2288
2289 pwfield = read_c0_pwfield();
2290 /* re-initialize the GDI field */
2291 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2292 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2293 #ifdef CONFIG_64BIT
2294 #if defined(CONFIG_48VMBITS) || !defined(CONFIG_PAGE_SIZE_64KB)
2295 /* re-initialize the MDI field */
2296 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2297 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2298 /* re-initialize the BDI field */
2299 pwfield &= ~MIPS_PWFIELD_BDI_MASK;
2300 pwfield |= MIPS_BASE_SHIFT << MIPS_PWFIELD_BDI_SHIFT;
2301 #endif
2302 #endif
2303 /* re-initialize the PTI field including the even/odd bit */
2304 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2305 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
2306 /* Set the PTEI right shift */
2307 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2308 pwfield |= ptei;
2309 write_c0_pwfield(pwfield);
2310 /* Check whether the PTEI value is supported */
2311 back_to_back_c0_hazard();
2312 pwfield = read_c0_pwfield();
2313 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2314 != ptei) {
2315 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2316 ptei);
2317 /*
2318 * Drop option to avoid HTW being enabled via another path
2319 * (eg htw_reset())
2320 */
2321 current_cpu_data.options2 &= ~MIPS_CPU_HTW;
2322 return;
2323 }
2324
2325 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2326 #ifdef CONFIG_64BIT
2327 pwsize |= MIPS_BASE_SIZE;
2328 pwsize |= MIPS_PWSIZE_PS;
2329 #if defined(CONFIG_48VMBITS) || !defined(CONFIG_PAGE_SIZE_64KB)
2330 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
2331 #endif
2332 #endif
2333 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
2334 write_c0_pwsize(pwsize);
2335
2336 /* Make sure everything is set before we enable the HTW */
2337 back_to_back_c0_hazard();
2338
2339 /* Don't enable HTW until PWBASE is set */
2340 pr_info("Hardware Page Table Walker is configured\n");
2341
2342 print_htw_config();
2343 }
2344
build_tlb_refill_handler(void)2345 void __cpuinit build_tlb_refill_handler(void)
2346 {
2347 /*
2348 * The refill handler is generated per-CPU, multi-node systems
2349 * may have local storage for it. The other handlers are only
2350 * needed once.
2351 */
2352 static int run_once = 0;
2353
2354 output_pgtable_bits_defines();
2355
2356 #ifdef CONFIG_64BIT
2357 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2358 #endif
2359
2360 switch (current_cpu_type()) {
2361 case CPU_R2000:
2362 case CPU_R3000:
2363 case CPU_R3000A:
2364 case CPU_R3081E:
2365 case CPU_TX3912:
2366 case CPU_TX3922:
2367 case CPU_TX3927:
2368 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
2369 if (cpu_has_local_ebase)
2370 build_r3000_tlb_refill_handler();
2371 if (!run_once) {
2372 if (!cpu_has_local_ebase)
2373 build_r3000_tlb_refill_handler();
2374 build_r3000_tlb_load_handler();
2375 build_r3000_tlb_store_handler();
2376 build_r3000_tlb_modify_handler();
2377 run_once++;
2378 }
2379 #else
2380 panic("No R3000 TLB refill handler");
2381 #endif
2382 break;
2383
2384 case CPU_R6000:
2385 case CPU_R6000A:
2386 panic("No R6000 TLB refill handler yet");
2387 break;
2388
2389 case CPU_R8000:
2390 panic("No R8000 TLB refill handler yet");
2391 break;
2392
2393 default:
2394 if (!run_once) {
2395 scratch_reg = allocate_kscratch();
2396 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2397 build_r4000_setup_pgd();
2398 #endif
2399 build_r4000_tlb_load_handler();
2400 build_r4000_tlb_store_handler();
2401 build_r4000_tlb_modify_handler();
2402 if (!cpu_has_local_ebase)
2403 build_r4000_tlb_refill_handler();
2404 run_once++;
2405 }
2406 if (cpu_has_local_ebase)
2407 build_r4000_tlb_refill_handler();
2408 if (cpu_has_htw)
2409 config_htw_params();
2410
2411 }
2412 }
2413
flush_tlb_handlers(void)2414 void __cpuinit flush_tlb_handlers(void)
2415 {
2416 local_flush_icache_range((unsigned long)handle_tlbl,
2417 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
2418 local_flush_icache_range((unsigned long)handle_tlbs,
2419 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
2420 local_flush_icache_range((unsigned long)handle_tlbm,
2421 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
2422 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
2423 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array,
2424 (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm));
2425 #endif
2426 }
2427