1 /*
2 * Samsung S5P Multi Format Codec v 5.0
3 *
4 * This file contains definitions of enums and structs used by the codec
5 * driver.
6 *
7 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
8 * Kamil Debski, <k.debski@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version
14 */
15
16 #ifndef S5P_MFC_COMMON_H_
17 #define S5P_MFC_COMMON_H_
18
19 #include <linux/platform_device.h>
20 #include <linux/videodev2.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/videobuf2-core.h>
25 #include "regs-mfc.h"
26 #include "regs-mfc-v6.h"
27
28 /* Definitions related to MFC memory */
29
30 /* Offset base used to differentiate between CAPTURE and OUTPUT
31 * while mmaping */
32 #define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
33
34 #define MFC_BANK1_ALLOC_CTX 0
35 #define MFC_BANK2_ALLOC_CTX 1
36
37 #define MFC_BANK1_ALIGN_ORDER 13
38 #define MFC_BANK2_ALIGN_ORDER 13
39 #define MFC_BASE_ALIGN_ORDER 17
40
41 #include <media/videobuf2-dma-contig.h>
42
s5p_mfc_mem_cookie(void * a,void * b)43 static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
44 {
45 /* Same functionality as the vb2_dma_contig_plane_paddr */
46 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
47
48 return *paddr;
49 }
50
51 /* MFC definitions */
52 #define MFC_MAX_EXTRA_DPB 5
53 #define MFC_MAX_BUFFERS 32
54 #define MFC_NUM_CONTEXTS 4
55 /* Interrupt timeout */
56 #define MFC_INT_TIMEOUT 2000
57 /* Busy wait timeout */
58 #define MFC_BW_TIMEOUT 500
59 /* Watchdog interval */
60 #define MFC_WATCHDOG_INTERVAL 1000
61 /* After how many executions watchdog should assume lock up */
62 #define MFC_WATCHDOG_CNT 10
63 #define MFC_NO_INSTANCE_SET -1
64 #define MFC_ENC_CAP_PLANE_COUNT 1
65 #define MFC_ENC_OUT_PLANE_COUNT 2
66 #define STUFF_BYTE 4
67 #define MFC_MAX_CTRLS 70
68
69 #define S5P_MFC_CODEC_NONE -1
70 #define S5P_MFC_CODEC_H264_DEC 0
71 #define S5P_MFC_CODEC_H264_MVC_DEC 1
72 #define S5P_MFC_CODEC_VC1_DEC 2
73 #define S5P_MFC_CODEC_MPEG4_DEC 3
74 #define S5P_MFC_CODEC_MPEG2_DEC 4
75 #define S5P_MFC_CODEC_H263_DEC 5
76 #define S5P_MFC_CODEC_VC1RCV_DEC 6
77 #define S5P_MFC_CODEC_VP8_DEC 7
78
79 #define S5P_MFC_CODEC_H264_ENC 20
80 #define S5P_MFC_CODEC_H264_MVC_ENC 21
81 #define S5P_MFC_CODEC_MPEG4_ENC 22
82 #define S5P_MFC_CODEC_H263_ENC 23
83
84 #define S5P_MFC_R2H_CMD_EMPTY 0
85 #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
86 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
87 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
88 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
89 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
90 #define S5P_MFC_R2H_CMD_SLEEP_RET 7
91 #define S5P_MFC_R2H_CMD_WAKEUP_RET 8
92 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
93 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
94 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
95 #define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
96 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
97 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
98 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
99 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
100 #define S5P_MFC_R2H_CMD_ERR_RET 32
101
102 #define mfc_read(dev, offset) readl(dev->regs_base + (offset))
103 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
104 (offset))
105
106 /**
107 * enum s5p_mfc_fmt_type - type of the pixelformat
108 */
109 enum s5p_mfc_fmt_type {
110 MFC_FMT_DEC,
111 MFC_FMT_ENC,
112 MFC_FMT_RAW,
113 };
114
115 /**
116 * enum s5p_mfc_node_type - The type of an MFC device node.
117 */
118 enum s5p_mfc_node_type {
119 MFCNODE_INVALID = -1,
120 MFCNODE_DECODER = 0,
121 MFCNODE_ENCODER = 1,
122 };
123
124 /**
125 * enum s5p_mfc_inst_type - The type of an MFC instance.
126 */
127 enum s5p_mfc_inst_type {
128 MFCINST_INVALID,
129 MFCINST_DECODER,
130 MFCINST_ENCODER,
131 };
132
133 /**
134 * enum s5p_mfc_inst_state - The state of an MFC instance.
135 */
136 enum s5p_mfc_inst_state {
137 MFCINST_FREE = 0,
138 MFCINST_INIT = 100,
139 MFCINST_GOT_INST,
140 MFCINST_HEAD_PARSED,
141 MFCINST_HEAD_PRODUCED,
142 MFCINST_BUFS_SET,
143 MFCINST_RUNNING,
144 MFCINST_FINISHING,
145 MFCINST_FINISHED,
146 MFCINST_RETURN_INST,
147 MFCINST_ERROR,
148 MFCINST_ABORT,
149 MFCINST_FLUSH,
150 MFCINST_RES_CHANGE_INIT,
151 MFCINST_RES_CHANGE_FLUSH,
152 MFCINST_RES_CHANGE_END,
153 };
154
155 /**
156 * enum s5p_mfc_queue_state - The state of buffer queue.
157 */
158 enum s5p_mfc_queue_state {
159 QUEUE_FREE,
160 QUEUE_BUFS_REQUESTED,
161 QUEUE_BUFS_QUERIED,
162 QUEUE_BUFS_MMAPED,
163 };
164
165 /**
166 * enum s5p_mfc_decode_arg - type of frame decoding
167 */
168 enum s5p_mfc_decode_arg {
169 MFC_DEC_FRAME,
170 MFC_DEC_LAST_FRAME,
171 MFC_DEC_RES_CHANGE,
172 };
173
174 #define MFC_BUF_FLAG_USED (1 << 0)
175 #define MFC_BUF_FLAG_EOS (1 << 1)
176
177 struct s5p_mfc_ctx;
178
179 /**
180 * struct s5p_mfc_buf - MFC buffer
181 */
182 struct s5p_mfc_buf {
183 struct list_head list;
184 struct vb2_buffer *b;
185 union {
186 struct {
187 size_t luma;
188 size_t chroma;
189 } raw;
190 size_t stream;
191 } cookie;
192 int flags;
193 };
194
195 /**
196 * struct s5p_mfc_pm - power management data structure
197 */
198 struct s5p_mfc_pm {
199 struct clk *clock;
200 struct clk *clock_gate;
201 atomic_t power;
202 struct device *device;
203 };
204
205 struct s5p_mfc_buf_size_v5 {
206 unsigned int h264_ctx;
207 unsigned int non_h264_ctx;
208 unsigned int dsc;
209 unsigned int shm;
210 };
211
212 struct s5p_mfc_buf_size_v6 {
213 unsigned int dev_ctx;
214 unsigned int h264_dec_ctx;
215 unsigned int other_dec_ctx;
216 unsigned int h264_enc_ctx;
217 unsigned int other_enc_ctx;
218 };
219
220 struct s5p_mfc_buf_size {
221 unsigned int fw;
222 unsigned int cpb;
223 void *priv;
224 };
225
226 struct s5p_mfc_buf_align {
227 unsigned int base;
228 };
229
230 struct s5p_mfc_variant {
231 unsigned int version;
232 unsigned int port_num;
233 struct s5p_mfc_buf_size *buf_size;
234 struct s5p_mfc_buf_align *buf_align;
235 char *fw_name;
236 };
237
238 /**
239 * struct s5p_mfc_priv_buf - represents internal used buffer
240 * @alloc: allocation-specific context for each buffer
241 * (videobuf2 allocator)
242 * @ofs: offset of each buffer, will be used for MFC
243 * @virt: kernel virtual address, only valid when the
244 * buffer accessed by driver
245 * @dma: DMA address, only valid when kernel DMA API used
246 * @size: size of the buffer
247 */
248 struct s5p_mfc_priv_buf {
249 void *alloc;
250 unsigned long ofs;
251 void *virt;
252 dma_addr_t dma;
253 size_t size;
254 };
255
256 /**
257 * struct s5p_mfc_dev - The struct containing driver internal parameters.
258 *
259 * @v4l2_dev: v4l2_device
260 * @vfd_dec: video device for decoding
261 * @vfd_enc: video device for encoding
262 * @plat_dev: platform device
263 * @mem_dev_l: child device of the left memory bank (0)
264 * @mem_dev_r: child device of the right memory bank (1)
265 * @regs_base: base address of the MFC hw registers
266 * @irq: irq resource
267 * @dec_ctrl_handler: control framework handler for decoding
268 * @enc_ctrl_handler: control framework handler for encoding
269 * @pm: power management control
270 * @variant: MFC hardware variant information
271 * @num_inst: couter of active MFC instances
272 * @irqlock: lock for operations on videobuf2 queues
273 * @condlock: lock for changing/checking if a context is ready to be
274 * processed
275 * @mfc_mutex: lock for video_device
276 * @int_cond: variable used by the waitqueue
277 * @int_type: type of last interrupt
278 * @int_err: error number for last interrupt
279 * @queue: waitqueue for waiting for completion of device commands
280 * @fw_size: size of firmware
281 * @fw_virt_addr: virtual firmware address
282 * @bank1: address of the beginning of bank 1 memory
283 * @bank2: address of the beginning of bank 2 memory
284 * @hw_lock: used for hardware locking
285 * @ctx: array of driver contexts
286 * @curr_ctx: number of the currently running context
287 * @ctx_work_bits: used to mark which contexts are waiting for hardware
288 * @watchdog_cnt: counter for the watchdog
289 * @watchdog_workqueue: workqueue for the watchdog
290 * @watchdog_work: worker for the watchdog
291 * @alloc_ctx: videobuf2 allocator contexts for two memory banks
292 * @enter_suspend: flag set when entering suspend
293 * @ctx_buf: common context memory (MFCv6)
294 * @warn_start: hardware error code from which warnings start
295 * @mfc_ops: ops structure holding HW operation function pointers
296 * @mfc_cmds: cmd structure holding HW commands function pointers
297 *
298 */
299 struct s5p_mfc_dev {
300 struct v4l2_device v4l2_dev;
301 struct video_device *vfd_dec;
302 struct video_device *vfd_enc;
303 struct platform_device *plat_dev;
304 struct device *mem_dev_l;
305 struct device *mem_dev_r;
306 void __iomem *regs_base;
307 int irq;
308 struct v4l2_ctrl_handler dec_ctrl_handler;
309 struct v4l2_ctrl_handler enc_ctrl_handler;
310 struct s5p_mfc_pm pm;
311 struct s5p_mfc_variant *variant;
312 int num_inst;
313 spinlock_t irqlock; /* lock when operating on videobuf2 queues */
314 spinlock_t condlock; /* lock when changing/checking if a context is
315 ready to be processed */
316 struct mutex mfc_mutex; /* video_device lock */
317 int int_cond;
318 int int_type;
319 unsigned int int_err;
320 wait_queue_head_t queue;
321 size_t fw_size;
322 void *fw_virt_addr;
323 dma_addr_t bank1;
324 dma_addr_t bank2;
325 unsigned long hw_lock;
326 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
327 int curr_ctx;
328 unsigned long ctx_work_bits;
329 atomic_t watchdog_cnt;
330 struct timer_list watchdog_timer;
331 struct workqueue_struct *watchdog_workqueue;
332 struct work_struct watchdog_work;
333 void *alloc_ctx[2];
334 unsigned long enter_suspend;
335
336 struct s5p_mfc_priv_buf ctx_buf;
337 int warn_start;
338 struct s5p_mfc_hw_ops *mfc_ops;
339 struct s5p_mfc_hw_cmds *mfc_cmds;
340 };
341
342 /**
343 * struct s5p_mfc_h264_enc_params - encoding parameters for h264
344 */
345 struct s5p_mfc_h264_enc_params {
346 enum v4l2_mpeg_video_h264_profile profile;
347 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
348 s8 loop_filter_alpha;
349 s8 loop_filter_beta;
350 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
351 u8 max_ref_pic;
352 u8 num_ref_pic_4p;
353 int _8x8_transform;
354 int rc_mb_dark;
355 int rc_mb_smooth;
356 int rc_mb_static;
357 int rc_mb_activity;
358 int vui_sar;
359 u8 vui_sar_idc;
360 u16 vui_ext_sar_width;
361 u16 vui_ext_sar_height;
362 int open_gop;
363 u16 open_gop_size;
364 u8 rc_frame_qp;
365 u8 rc_min_qp;
366 u8 rc_max_qp;
367 u8 rc_p_frame_qp;
368 u8 rc_b_frame_qp;
369 enum v4l2_mpeg_video_h264_level level_v4l2;
370 int level;
371 u16 cpb_size;
372 int interlace;
373 u8 hier_qp;
374 u8 hier_qp_type;
375 u8 hier_qp_layer;
376 u8 hier_qp_layer_qp[7];
377 u8 sei_frame_packing;
378 u8 sei_fp_curr_frame_0;
379 u8 sei_fp_arrangement_type;
380
381 u8 fmo;
382 u8 fmo_map_type;
383 u8 fmo_slice_grp;
384 u8 fmo_chg_dir;
385 u32 fmo_chg_rate;
386 u32 fmo_run_len[4];
387 u8 aso;
388 u32 aso_slice_order[8];
389 };
390
391 /**
392 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
393 */
394 struct s5p_mfc_mpeg4_enc_params {
395 /* MPEG4 Only */
396 enum v4l2_mpeg_video_mpeg4_profile profile;
397 int quarter_pixel;
398 /* Common for MPEG4, H263 */
399 u16 vop_time_res;
400 u16 vop_frm_delta;
401 u8 rc_frame_qp;
402 u8 rc_min_qp;
403 u8 rc_max_qp;
404 u8 rc_p_frame_qp;
405 u8 rc_b_frame_qp;
406 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
407 int level;
408 };
409
410 /**
411 * struct s5p_mfc_enc_params - general encoding parameters
412 */
413 struct s5p_mfc_enc_params {
414 u16 width;
415 u16 height;
416
417 u16 gop_size;
418 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
419 u16 slice_mb;
420 u32 slice_bit;
421 u16 intra_refresh_mb;
422 int pad;
423 u8 pad_luma;
424 u8 pad_cb;
425 u8 pad_cr;
426 int rc_frame;
427 int rc_mb;
428 u32 rc_bitrate;
429 u16 rc_reaction_coeff;
430 u16 vbv_size;
431 u32 vbv_delay;
432
433 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
434 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
435 int fixed_target_bit;
436
437 u8 num_b_frame;
438 u32 rc_framerate_num;
439 u32 rc_framerate_denom;
440
441 struct {
442 struct s5p_mfc_h264_enc_params h264;
443 struct s5p_mfc_mpeg4_enc_params mpeg4;
444 } codec;
445
446 };
447
448 /**
449 * struct s5p_mfc_codec_ops - codec ops, used by encoding
450 */
451 struct s5p_mfc_codec_ops {
452 /* initialization routines */
453 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
454 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
455 /* execution routines */
456 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
457 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
458 };
459
460 #define call_cop(c, op, args...) \
461 (((c)->c_ops->op) ? \
462 ((c)->c_ops->op(args)) : 0)
463
464 /**
465 * struct s5p_mfc_ctx - This struct contains the instance context
466 *
467 * @dev: pointer to the s5p_mfc_dev of the device
468 * @fh: struct v4l2_fh
469 * @num: number of the context that this structure describes
470 * @int_cond: variable used by the waitqueue
471 * @int_type: type of the last interrupt
472 * @int_err: error number received from MFC hw in the interrupt
473 * @queue: waitqueue that can be used to wait for this context to
474 * finish
475 * @src_fmt: source pixelformat information
476 * @dst_fmt: destination pixelformat information
477 * @vq_src: vb2 queue for source buffers
478 * @vq_dst: vb2 queue for destination buffers
479 * @src_queue: driver internal queue for source buffers
480 * @dst_queue: driver internal queue for destination buffers
481 * @src_queue_cnt: number of buffers queued on the source internal queue
482 * @dst_queue_cnt: number of buffers queued on the dest internal queue
483 * @type: type of the instance - decoder or encoder
484 * @state: state of the context
485 * @inst_no: number of hw instance associated with the context
486 * @img_width: width of the image that is decoded or encoded
487 * @img_height: height of the image that is decoded or encoded
488 * @buf_width: width of the buffer for processed image
489 * @buf_height: height of the buffer for processed image
490 * @luma_size: size of a luma plane
491 * @chroma_size: size of a chroma plane
492 * @mv_size: size of a motion vectors buffer
493 * @consumed_stream: number of bytes that have been used so far from the
494 * decoding buffer
495 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
496 * flushed
497 * @head_processed: flag mentioning whether the header data is processed
498 * completely or not
499 * @bank1: handle to memory allocated for temporary buffers from
500 * memory bank 1
501 * @bank2: handle to memory allocated for temporary buffers from
502 * memory bank 2
503 * @capture_state: state of the capture buffers queue
504 * @output_state: state of the output buffers queue
505 * @src_bufs: information on allocated source buffers
506 * @dst_bufs: information on allocated destination buffers
507 * @sequence: counter for the sequence number for v4l2
508 * @dec_dst_flag: flags for buffers queued in the hardware
509 * @dec_src_buf_size: size of the buffer for source buffers in decoding
510 * @codec_mode: number of codec mode used by MFC hw
511 * @slice_interface: slice interface flag
512 * @loop_filter_mpeg4: loop filter for MPEG4 flag
513 * @display_delay: value of the display delay for H264
514 * @display_delay_enable: display delay for H264 enable flag
515 * @after_packed_pb: flag used to track buffer when stream is in
516 * Packed PB format
517 * @sei_fp_parse: enable/disable parsing of frame packing SEI information
518 * @dpb_count: count of the DPB buffers required by MFC hw
519 * @total_dpb_count: count of DPB buffers with additional buffers
520 * requested by the application
521 * @ctx: context buffer information
522 * @dsc: descriptor buffer information
523 * @shm: shared memory buffer information
524 * @mv_count: number of MV buffers allocated for decoding
525 * @enc_params: encoding parameters for MFC
526 * @enc_dst_buf_size: size of the buffers for encoder output
527 * @luma_dpb_size: dpb buffer size for luma
528 * @chroma_dpb_size: dpb buffer size for chroma
529 * @me_buffer_size: size of the motion estimation buffer
530 * @tmv_buffer_size: size of temporal predictor motion vector buffer
531 * @frame_type: used to force the type of the next encoded frame
532 * @ref_queue: list of the reference buffers for encoding
533 * @ref_queue_cnt: number of the buffers in the reference list
534 * @c_ops: ops for encoding
535 * @ctrls: array of controls, used when adding controls to the
536 * v4l2 control framework
537 * @ctrl_handler: handler for v4l2 framework
538 */
539 struct s5p_mfc_ctx {
540 struct s5p_mfc_dev *dev;
541 struct v4l2_fh fh;
542
543 int num;
544
545 int int_cond;
546 int int_type;
547 unsigned int int_err;
548 wait_queue_head_t queue;
549
550 struct s5p_mfc_fmt *src_fmt;
551 struct s5p_mfc_fmt *dst_fmt;
552
553 struct vb2_queue vq_src;
554 struct vb2_queue vq_dst;
555
556 struct list_head src_queue;
557 struct list_head dst_queue;
558
559 unsigned int src_queue_cnt;
560 unsigned int dst_queue_cnt;
561
562 enum s5p_mfc_inst_type type;
563 enum s5p_mfc_inst_state state;
564 int inst_no;
565
566 /* Image parameters */
567 int img_width;
568 int img_height;
569 int buf_width;
570 int buf_height;
571
572 int luma_size;
573 int chroma_size;
574 int mv_size;
575
576 unsigned long consumed_stream;
577
578 unsigned int dpb_flush_flag;
579 unsigned int head_processed;
580
581 struct s5p_mfc_priv_buf bank1;
582 struct s5p_mfc_priv_buf bank2;
583
584 enum s5p_mfc_queue_state capture_state;
585 enum s5p_mfc_queue_state output_state;
586
587 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
588 int src_bufs_cnt;
589 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
590 int dst_bufs_cnt;
591
592 unsigned int sequence;
593 unsigned long dec_dst_flag;
594 size_t dec_src_buf_size;
595
596 /* Control values */
597 int codec_mode;
598 int slice_interface;
599 int loop_filter_mpeg4;
600 int display_delay;
601 int display_delay_enable;
602 int after_packed_pb;
603 int sei_fp_parse;
604
605 int pb_count;
606 int total_dpb_count;
607 int mv_count;
608 /* Buffers */
609 struct s5p_mfc_priv_buf ctx;
610 struct s5p_mfc_priv_buf dsc;
611 struct s5p_mfc_priv_buf shm;
612
613 struct s5p_mfc_enc_params enc_params;
614
615 size_t enc_dst_buf_size;
616 size_t luma_dpb_size;
617 size_t chroma_dpb_size;
618 size_t me_buffer_size;
619 size_t tmv_buffer_size;
620
621 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
622
623 struct list_head ref_queue;
624 unsigned int ref_queue_cnt;
625
626 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
627 union {
628 unsigned int mb;
629 unsigned int bits;
630 } slice_size;
631
632 struct s5p_mfc_codec_ops *c_ops;
633
634 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
635 struct v4l2_ctrl_handler ctrl_handler;
636 unsigned int frame_tag;
637 size_t scratch_buf_size;
638 };
639
640 /*
641 * struct s5p_mfc_fmt - structure used to store information about pixelformats
642 * used by the MFC
643 */
644 struct s5p_mfc_fmt {
645 char *name;
646 u32 fourcc;
647 u32 codec_mode;
648 enum s5p_mfc_fmt_type type;
649 u32 num_planes;
650 };
651
652 /**
653 * struct mfc_control - structure used to store information about MFC controls
654 * it is used to initialize the control framework.
655 */
656 struct mfc_control {
657 __u32 id;
658 enum v4l2_ctrl_type type;
659 __u8 name[32]; /* Whatever */
660 __s32 minimum; /* Note signedness */
661 __s32 maximum;
662 __s32 step;
663 __u32 menu_skip_mask;
664 __s32 default_value;
665 __u32 flags;
666 __u32 reserved[2];
667 __u8 is_volatile;
668 };
669
670 /* Macro for making hardware specific calls */
671 #define s5p_mfc_hw_call(f, op, args...) \
672 ((f && f->op) ? f->op(args) : -ENODEV)
673
674 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
675 #define ctrl_to_ctx(__ctrl) \
676 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
677
678 void clear_work_bit(struct s5p_mfc_ctx *ctx);
679 void set_work_bit(struct s5p_mfc_ctx *ctx);
680 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
681 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
682
683 #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
684 (dev->variant->port_num ? 1 : 0) : 0) : 0)
685 #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
686 #define IS_MFCV6(dev) (dev->variant->version >= 0x60 ? 1 : 0)
687
688 #endif /* S5P_MFC_COMMON_H_ */
689