1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #ifndef __QLCNIC_HW_H 9 #define __QLCNIC_HW_H 10 11 /* Common registers in 83xx and 82xx */ 12 enum qlcnic_regs { 13 QLCNIC_PEG_HALT_STATUS1 = 0, 14 QLCNIC_PEG_HALT_STATUS2, 15 QLCNIC_PEG_ALIVE_COUNTER, 16 QLCNIC_FLASH_LOCK_OWNER, 17 QLCNIC_FW_CAPABILITIES, 18 QLCNIC_CRB_DRV_ACTIVE, 19 QLCNIC_CRB_DEV_STATE, 20 QLCNIC_CRB_DRV_STATE, 21 QLCNIC_CRB_DRV_SCRATCH, 22 QLCNIC_CRB_DEV_PARTITION_INFO, 23 QLCNIC_CRB_DRV_IDC_VER, 24 QLCNIC_FW_VERSION_MAJOR, 25 QLCNIC_FW_VERSION_MINOR, 26 QLCNIC_FW_VERSION_SUB, 27 QLCNIC_CRB_DEV_NPAR_STATE, 28 QLCNIC_FW_IMG_VALID, 29 QLCNIC_CMDPEG_STATE, 30 QLCNIC_RCVPEG_STATE, 31 QLCNIC_ASIC_TEMP, 32 QLCNIC_FW_API, 33 QLCNIC_DRV_OP_MODE, 34 QLCNIC_FLASH_LOCK, 35 QLCNIC_FLASH_UNLOCK, 36 }; 37 38 /* Read from an address offset from BAR0, existing registers */ 39 #define QLC_SHARED_REG_RD32(a, addr) \ 40 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr])) 41 42 /* Write to an address offset from BAR0, existing registers */ 43 #define QLC_SHARED_REG_WR32(a, addr, value) \ 44 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr])) 45 46 /* Read from a direct address offset from BAR0, additional registers */ 47 #define QLCRDX(ahw, addr) \ 48 readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])) 49 50 /* Write to a direct address offset from BAR0, additional registers */ 51 #define QLCWRX(ahw, addr, value) \ 52 writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))) 53 54 #define QLCNIC_CMD_CONFIGURE_IP_ADDR 0x1 55 #define QLCNIC_CMD_CONFIG_INTRPT 0x2 56 #define QLCNIC_CMD_CREATE_RX_CTX 0x7 57 #define QLCNIC_CMD_DESTROY_RX_CTX 0x8 58 #define QLCNIC_CMD_CREATE_TX_CTX 0x9 59 #define QLCNIC_CMD_DESTROY_TX_CTX 0xa 60 #define QLCNIC_CMD_CONFIGURE_LRO 0xC 61 #define QLCNIC_CMD_CONFIGURE_MAC_LEARNING 0xD 62 #define QLCNIC_CMD_GET_STATISTICS 0xF 63 #define QLCNIC_CMD_INTRPT_TEST 0x11 64 #define QLCNIC_CMD_SET_MTU 0x12 65 #define QLCNIC_CMD_READ_PHY 0x13 66 #define QLCNIC_CMD_WRITE_PHY 0x14 67 #define QLCNIC_CMD_READ_HW_REG 0x15 68 #define QLCNIC_CMD_GET_FLOW_CTL 0x16 69 #define QLCNIC_CMD_SET_FLOW_CTL 0x17 70 #define QLCNIC_CMD_READ_MAX_MTU 0x18 71 #define QLCNIC_CMD_READ_MAX_LRO 0x19 72 #define QLCNIC_CMD_MAC_ADDRESS 0x1f 73 #define QLCNIC_CMD_GET_PCI_INFO 0x20 74 #define QLCNIC_CMD_GET_NIC_INFO 0x21 75 #define QLCNIC_CMD_SET_NIC_INFO 0x22 76 #define QLCNIC_CMD_GET_ESWITCH_CAPABILITY 0x24 77 #define QLCNIC_CMD_TOGGLE_ESWITCH 0x25 78 #define QLCNIC_CMD_GET_ESWITCH_STATUS 0x26 79 #define QLCNIC_CMD_SET_PORTMIRRORING 0x27 80 #define QLCNIC_CMD_CONFIGURE_ESWITCH 0x28 81 #define QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG 0x29 82 #define QLCNIC_CMD_GET_ESWITCH_STATS 0x2a 83 #define QLCNIC_CMD_CONFIG_PORT 0x2e 84 #define QLCNIC_CMD_TEMP_SIZE 0x2f 85 #define QLCNIC_CMD_GET_TEMP_HDR 0x30 86 #define QLCNIC_CMD_BC_EVENT_SETUP 0x31 87 #define QLCNIC_CMD_CONFIG_VPORT 0x32 88 #define QLCNIC_CMD_GET_MAC_STATS 0x37 89 #define QLCNIC_CMD_SET_DRV_VER 0x38 90 #define QLCNIC_CMD_CONFIGURE_RSS 0x41 91 #define QLCNIC_CMD_CONFIG_INTR_COAL 0x43 92 #define QLCNIC_CMD_CONFIGURE_LED 0x44 93 #define QLCNIC_CMD_CONFIG_MAC_VLAN 0x45 94 #define QLCNIC_CMD_GET_LINK_EVENT 0x48 95 #define QLCNIC_CMD_CONFIGURE_MAC_RX_MODE 0x49 96 #define QLCNIC_CMD_CONFIGURE_HW_LRO 0x4A 97 #define QLCNIC_CMD_INIT_NIC_FUNC 0x60 98 #define QLCNIC_CMD_STOP_NIC_FUNC 0x61 99 #define QLCNIC_CMD_IDC_ACK 0x63 100 #define QLCNIC_CMD_SET_PORT_CONFIG 0x66 101 #define QLCNIC_CMD_GET_PORT_CONFIG 0x67 102 #define QLCNIC_CMD_GET_LINK_STATUS 0x68 103 #define QLCNIC_CMD_SET_LED_CONFIG 0x69 104 #define QLCNIC_CMD_GET_LED_CONFIG 0x6A 105 #define QLCNIC_CMD_ADD_RCV_RINGS 0x0B 106 107 #define QLCNIC_INTRPT_INTX 1 108 #define QLCNIC_INTRPT_MSIX 3 109 #define QLCNIC_INTRPT_ADD 1 110 #define QLCNIC_INTRPT_DEL 2 111 112 #define QLCNIC_GET_CURRENT_MAC 1 113 #define QLCNIC_SET_STATION_MAC 2 114 #define QLCNIC_GET_DEFAULT_MAC 3 115 #define QLCNIC_GET_FAC_DEF_MAC 4 116 #define QLCNIC_SET_FAC_DEF_MAC 5 117 118 #define QLCNIC_MBX_LINK_EVENT 0x8001 119 #define QLCNIC_MBX_BC_EVENT 0x8002 120 #define QLCNIC_MBX_COMP_EVENT 0x8100 121 #define QLCNIC_MBX_REQUEST_EVENT 0x8101 122 #define QLCNIC_MBX_TIME_EXTEND_EVENT 0x8102 123 #define QLCNIC_MBX_SFP_INSERT_EVENT 0x8130 124 #define QLCNIC_MBX_SFP_REMOVE_EVENT 0x8131 125 126 struct qlcnic_mailbox_metadata { 127 u32 cmd; 128 u32 in_args; 129 u32 out_args; 130 }; 131 132 /* Mailbox ownership */ 133 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1)) 134 135 #define QLCNIC_SET_OWNER 1 136 #define QLCNIC_CLR_OWNER 0 137 #define QLCNIC_MBX_TIMEOUT 5000 138 139 #define QLCNIC_MBX_RSP_OK 1 140 #define QLCNIC_MBX_PORT_RSP_OK 0x1a 141 #define QLCNIC_MBX_ASYNC_EVENT BIT_15 142 143 struct qlcnic_pci_info; 144 struct qlcnic_info; 145 struct qlcnic_cmd_args; 146 struct ethtool_stats; 147 struct pci_device_id; 148 struct qlcnic_host_sds_ring; 149 struct qlcnic_host_tx_ring; 150 struct qlcnic_host_tx_ring; 151 struct qlcnic_hardware_context; 152 struct qlcnic_adapter; 153 154 int qlcnic_82xx_start_firmware(struct qlcnic_adapter *); 155 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong); 156 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32); 157 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int); 158 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32); 159 int qlcnic_82xx_napi_add(struct qlcnic_adapter *adapter, 160 struct net_device *netdev); 161 void qlcnic_82xx_change_filter(struct qlcnic_adapter *adapter, 162 u64 *uaddr, u16 vlan_id); 163 void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter); 164 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int); 165 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter, 166 __be32, int); 167 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int); 168 void qlcnic_82xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); 169 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8); 170 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *, u8); 171 void qlcnic_82xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 172 void qlcnic_82xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 173 void qlcnic_82xx_dev_request_reset(struct qlcnic_adapter *, u32); 174 int qlcnic_82xx_setup_intr(struct qlcnic_adapter *, u8); 175 irqreturn_t qlcnic_82xx_clear_legacy_intr(struct qlcnic_adapter *); 176 int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter, 177 struct qlcnic_cmd_args *); 178 int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *); 179 int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *, 180 struct qlcnic_host_tx_ring *tx_ring, int); 181 void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *); 182 void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *, 183 struct qlcnic_host_tx_ring *); 184 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8); 185 int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *, u8*); 186 int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); 187 int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); 188 int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*); 189 int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *, 190 struct qlcnic_adapter *, u32); 191 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32); 192 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *); 193 int qlcnic_82xx_config_led(struct qlcnic_adapter *, u32, u32); 194 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *); 195 int qlcnic_82xx_api_lock(struct qlcnic_adapter *); 196 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *); 197 void qlcnic_82xx_napi_enable(struct qlcnic_adapter *); 198 void qlcnic_82xx_napi_disable(struct qlcnic_adapter *); 199 void qlcnic_82xx_napi_del(struct qlcnic_adapter *); 200 #endif /* __QLCNIC_HW_H_ */ 201