1 /* Driver for Realtek RTS51xx USB card reader 2 * Header file 3 * 4 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2, or (at your option) any 9 * later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 * Author: 20 * wwang (wei_wang@realsil.com.cn) 21 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 22 * Maintainer: 23 * Edwin Rong (edwin_rong@realsil.com.cn) 24 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 25 */ 26 27 #ifndef __RTS51X_SD_H 28 #define __RTS51X_SD_H 29 30 #include "rts51x_chip.h" 31 32 #define SD_MAX_RETRY_COUNT 3 33 34 #define SUPPORT_VOLTAGE 0x003C0000 35 36 #define SD_RESET_FAIL 0x01 37 #define MMC_RESET_FAIL 0x02 38 39 /* Error Code */ 40 #define SD_NO_ERROR 0x0 41 #define SD_CRC_ERR 0x80 42 #define SD_TO_ERR 0x40 43 #define SD_NO_CARD 0x20 44 #define SD_BUSY 0x10 45 #define SD_STS_ERR 0x08 46 #define SD_RSP_TIMEOUT 0x04 47 48 /* MMC/SD Command Index */ 49 /* Basic command (class 0) */ 50 #define GO_IDLE_STATE 0 51 #define SEND_OP_COND 1 /* reserved for SD */ 52 #define ALL_SEND_CID 2 53 #define SET_RELATIVE_ADDR 3 54 #define SEND_RELATIVE_ADDR 3 55 #define SET_DSR 4 56 #define IO_SEND_OP_COND 5 57 #define SWITCH 6 58 #define SELECT_CARD 7 59 #define DESELECT_CARD 7 60 /* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec 61 * while is "SEND_IF_COND" for SD 2.0 */ 62 #define SEND_EXT_CSD 8 63 #define SEND_IF_COND 8 64 /* end */ 65 #define SEND_CSD 9 66 #define SEND_CID 10 67 #define VOLTAGE_SWITCH 11 68 #define READ_DAT_UTIL_STOP 11 /* reserved for SD */ 69 #define STOP_TRANSMISSION 12 70 #define SEND_STATUS 13 71 #define GO_INACTIVE_STATE 15 72 73 /* Block oriented read commands (class 2) */ 74 #define SET_BLOCKLEN 16 75 #define READ_SINGLE_BLOCK 17 76 #define READ_MULTIPLE_BLOCK 18 77 #define SEND_TUNING_PATTERN 19 78 79 /* Bus Width Test */ 80 #define BUSTEST_R 14 81 #define BUSTEST_W 19 82 /* end */ 83 84 /* Block oriented write commands (class 4) */ 85 #define WRITE_BLOCK 24 86 #define WRITE_MULTIPLE_BLOCK 25 87 #define PROGRAM_CSD 27 88 89 /* Erase commands */ 90 #define ERASE_WR_BLK_START 32 91 #define ERASE_WR_BLK_END 33 92 #define ERASE_CMD 38 93 94 /* Block Oriented Write Protection Commands */ 95 #define LOCK_UNLOCK 42 96 97 #define IO_RW_DIRECT 52 98 99 /* Application specific commands (class 8) */ 100 #define APP_CMD 55 101 #define GEN_CMD 56 102 103 /* SD Application command Index */ 104 #define SET_BUS_WIDTH 6 105 #define SD_STATUS 13 106 #define SEND_NUM_WR_BLOCKS 22 107 #define SET_WR_BLK_ERASE_COUNT 23 108 #define SD_APP_OP_COND 41 109 #define SET_CLR_CARD_DETECT 42 110 #define SEND_SCR 51 111 112 /* SD TIMEOUT function return error */ 113 #define SD_READ_COMPLETE 0x00 114 #define SD_READ_TO 0x01 115 #define SD_READ_ADVENCE 0x02 116 117 /* SD v1.1 CMD6 SWITCH function */ 118 #define SD_CHECK_MODE 0x00 119 #define SD_SWITCH_MODE 0x80 120 #define SD_FUNC_GROUP_1 0x01 121 #define SD_FUNC_GROUP_2 0x02 122 #define SD_FUNC_GROUP_3 0x03 123 #define SD_FUNC_GROUP_4 0x04 124 #define SD_CHECK_SPEC_V1_1 0xFF 125 126 /* SD Command Argument */ 127 #define NO_ARGUMENT 0x00 128 #define CHECK_PATTERN 0x000000AA 129 #define VOLTAGE_SUPPLY_RANGE 0x00000100 /* 2.7~3.6V */ 130 #define SUPPORT_HIGH_AND_EXTENDED_CAPACITY 0x40000000 131 #define SUPPORT_MAX_POWER_PERMANCE 0x10000000 132 #define SUPPORT_1V8 0x01000000 133 134 /* Switch Command Error Code */ 135 #define SWTICH_NO_ERR 0x00 136 #define CARD_NOT_EXIST 0x01 137 #define SPEC_NOT_SUPPORT 0x02 138 #define CHECK_MODE_ERR 0x03 139 #define CHECK_NOT_READY 0x04 140 #define SWITCH_CRC_ERR 0x05 141 #define SWITCH_MODE_ERR 0x06 142 #define SWITCH_PASS 0x07 143 144 /* Function Group Definition */ 145 /* Function Group 1 */ 146 #define HS_SUPPORT 0x01 147 #define SDR50_SUPPORT 0x02 148 #define SDR104_SUPPORT 0x03 149 #define DDR50_SUPPORT 0x04 150 #define HS_SUPPORT_MASK 0x02 151 #define SDR50_SUPPORT_MASK 0x04 152 #define SDR104_SUPPORT_MASK 0x08 153 #define DDR50_SUPPORT_MASK 0x10 154 #define HS_QUERY_SWITCH_OK 0x01 155 #define SDR50_QUERY_SWITCH_OK 0x02 156 #define SDR104_QUERY_SWITCH_OK 0x03 157 #define DDR50_QUERY_SWITCH_OK 0x04 158 #define HS_SWITCH_BUSY 0x02 159 #define SDR50_SWITCH_BUSY 0x04 160 #define SDR104_SWITCH_BUSY 0x08 161 #define DDR50_SWITCH_BUSY 0x10 162 #define FUNCTION_GROUP1_SUPPORT_OFFSET 0x0D 163 #define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET 0x10 164 #define FUNCTION_GROUP1_CHECK_BUSY_OFFSET 0x1D 165 /* Function Group 3 */ 166 #define DRIVING_TYPE_A 0x01 167 #define DRIVING_TYPE_B 0x00 168 #define DRIVING_TYPE_C 0x02 169 #define DRIVING_TYPE_D 0x03 170 #define DRIVING_TYPE_A_MASK 0x02 171 #define DRIVING_TYPE_B_MASK 0x01 172 #define DRIVING_TYPE_C_MASK 0x04 173 #define DRIVING_TYPE_D_MASK 0x08 174 #define TYPE_A_QUERY_SWITCH_OK 0x01 175 #define TYPE_B_QUERY_SWITCH_OK 0x00 176 #define TYPE_C_QUERY_SWITCH_OK 0x02 177 #define TYPE_D_QUERY_SWITCH_OK 0x03 178 #define TYPE_A_SWITCH_BUSY 0x02 179 #define TYPE_B_SWITCH_BUSY 0x01 180 #define TYPE_C_SWITCH_BUSY 0x04 181 #define TYPE_D_SWITCH_BUSY 0x08 182 #define FUNCTION_GROUP3_SUPPORT_OFFSET 0x09 183 #define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET 0x0F 184 #define FUNCTION_GROUP3_CHECK_BUSY_OFFSET 0x19 185 /* Function Group 4 */ 186 #define CURRENT_LIMIT_200 0x00 187 #define CURRENT_LIMIT_400 0x01 188 #define CURRENT_LIMIT_600 0x02 189 #define CURRENT_LIMIT_800 0x03 190 #define CURRENT_LIMIT_200_MASK 0x01 191 #define CURRENT_LIMIT_400_MASK 0x02 192 #define CURRENT_LIMIT_600_MASK 0x04 193 #define CURRENT_LIMIT_800_MASK 0x08 194 #define CURRENT_LIMIT_200_QUERY_SWITCH_OK 0x00 195 #define CURRENT_LIMIT_400_QUERY_SWITCH_OK 0x01 196 #define CURRENT_LIMIT_600_QUERY_SWITCH_OK 0x02 197 #define CURRENT_LIMIT_800_QUERY_SWITCH_OK 0x03 198 #define CURRENT_LIMIT_200_SWITCH_BUSY 0x01 199 #define CURRENT_LIMIT_400_SWITCH_BUSY 0x02 200 #define CURRENT_LIMIT_600_SWITCH_BUSY 0x04 201 #define CURRENT_LIMIT_800_SWITCH_BUSY 0x08 202 #define FUNCTION_GROUP4_SUPPORT_OFFSET 0x07 203 #define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET 0x0F 204 #define FUNCTION_GROUP4_CHECK_BUSY_OFFSET 0x17 205 /* Switch Function Status Offset */ 206 #define DATA_STRUCTURE_VER_OFFSET 0x11 /* The high offset */ 207 #define MAX_PHASE 15 208 /* #define TOTAL_READ_PHASE 0x20 */ 209 /* #define TOTAL_WRITE_PHASE 0x20 */ 210 /* MMC v4.0 */ 211 /* #define MMC_52MHZ_SPEED 0x0001 */ 212 /* #define MMC_26MHZ_SPEED 0x0002 */ 213 #define MMC_8BIT_BUS 0x0010 214 #define MMC_4BIT_BUS 0x0020 215 /* #define MMC_SECTOR_MODE 0x0100 */ 216 #define MMC_SWITCH_ERR 0x80 217 /* Tuning direction RX or TX */ 218 #define TUNE_TX 0x00 219 #define TUNE_RX 0x01 220 /* For Change_DCM_FreqMode Function */ 221 #define CHANGE_TX 0x00 222 #define CHANGE_RX 0x01 223 #define DCM_HIGH_FREQUENCY_MODE 0x00 224 #define DCM_LOW_FREQUENCY_MODE 0x01 225 #define DCM_HIGH_FREQUENCY_MODE_SET 0x0C 226 #define DCM_Low_FREQUENCY_MODE_SET 0x00 227 /* For Change_FPGA_SSCClock Function */ 228 #define MULTIPLY_BY_1 0x00 229 #define MULTIPLY_BY_2 0x01 230 #define MULTIPLY_BY_3 0x02 231 #define MULTIPLY_BY_4 0x03 232 #define MULTIPLY_BY_5 0x04 233 #define MULTIPLY_BY_6 0x05 234 #define MULTIPLY_BY_7 0x06 235 #define MULTIPLY_BY_8 0x07 236 #define MULTIPLY_BY_9 0x08 237 #define MULTIPLY_BY_10 0x09 238 #define DIVIDE_BY_2 0x01 239 #define DIVIDE_BY_3 0x02 240 #define DIVIDE_BY_4 0x03 241 #define DIVIDE_BY_5 0x04 242 #define DIVIDE_BY_6 0x05 243 #define DIVIDE_BY_7 0x06 244 #define DIVIDE_BY_8 0x07 245 #define DIVIDE_BY_9 0x08 246 #define DIVIDE_BY_10 0x09 247 #define CHECK_SD_TRANS_FAIL(chip, retval) \ 248 (((retval) != STATUS_SUCCESS) || \ 249 (chip->rsp_buf[0] & SD_TRANSFER_ERR)) 250 /* SD Tuning Data Structure */ 251 /* Record continuous timing phase path */ 252 struct timing_phase_path { 253 int start; 254 int end; 255 int mid; 256 int len; 257 }; 258 259 int rts51x_sd_select_card(struct rts51x_chip *chip, int select); 260 int rts51x_reset_sd_card(struct rts51x_chip *chip); 261 int rts51x_sd_switch_clock(struct rts51x_chip *chip); 262 int rts51x_sd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector, 263 u16 sector_cnt); 264 void rts51x_sd_cleanup_work(struct rts51x_chip *chip); 265 int rts51x_release_sd_card(struct rts51x_chip *chip); 266 267 #ifdef SUPPORT_CPRM 268 extern int reset_sd(struct rts51x_chip *chip); 269 extern int sd_check_data0_status(struct rts51x_chip *chip); 270 extern int sd_read_data(struct rts51x_chip *chip, u8 trans_mode, u8 *cmd, 271 int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width, 272 u8 *buf, int buf_len, int timeout); 273 #endif 274 275 #endif /* __RTS51X_SD_H */ 276