1 /*
2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 *
6 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/initval.h>
35 #include <sound/soc.h>
36 #include <sound/dmaengine_pcm.h>
37
38 #include <linux/platform_data/asoc-ti-mcbsp.h>
39 #include "mcbsp.h"
40 #include "omap-mcbsp.h"
41
42 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
43
44 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
45 xhandler_get, xhandler_put) \
46 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
47 .info = omap_mcbsp_st_info_volsw, \
48 .get = xhandler_get, .put = xhandler_put, \
49 .private_value = (unsigned long) &(struct soc_mixer_control) \
50 {.min = xmin, .max = xmax} }
51
52 enum {
53 OMAP_MCBSP_WORD_8 = 0,
54 OMAP_MCBSP_WORD_12,
55 OMAP_MCBSP_WORD_16,
56 OMAP_MCBSP_WORD_20,
57 OMAP_MCBSP_WORD_24,
58 OMAP_MCBSP_WORD_32,
59 };
60
61 /*
62 * Stream DMA parameters. DMA request line and port address are set runtime
63 * since they are different between OMAP1 and later OMAPs
64 */
omap_mcbsp_set_threshold(struct snd_pcm_substream * substream,unsigned int packet_size)65 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
66 unsigned int packet_size)
67 {
68 struct snd_soc_pcm_runtime *rtd = substream->private_data;
69 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
70 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
71 int words;
72
73 /*
74 * Configure McBSP threshold based on either:
75 * packet_size, when the sDMA is in packet mode, or based on the
76 * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
77 * for mono streams.
78 */
79 if (packet_size)
80 words = packet_size;
81 else
82 words = 1;
83
84 /* Configure McBSP internal buffer usage */
85 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
86 omap_mcbsp_set_tx_threshold(mcbsp, words);
87 else
88 omap_mcbsp_set_rx_threshold(mcbsp, words);
89 }
90
omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params * params,struct snd_pcm_hw_rule * rule)91 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
92 struct snd_pcm_hw_rule *rule)
93 {
94 struct snd_interval *buffer_size = hw_param_interval(params,
95 SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
96 struct snd_interval *channels = hw_param_interval(params,
97 SNDRV_PCM_HW_PARAM_CHANNELS);
98 struct omap_mcbsp *mcbsp = rule->private;
99 struct snd_interval frames;
100 int size;
101
102 snd_interval_any(&frames);
103 size = mcbsp->pdata->buffer_size;
104
105 frames.min = size / channels->min;
106 frames.integer = 1;
107 return snd_interval_refine(buffer_size, &frames);
108 }
109
omap_mcbsp_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)110 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
111 struct snd_soc_dai *cpu_dai)
112 {
113 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
114 int err = 0;
115
116 if (!cpu_dai->active)
117 err = omap_mcbsp_request(mcbsp);
118
119 /*
120 * OMAP3 McBSP FIFO is word structured.
121 * McBSP2 has 1024 + 256 = 1280 word long buffer,
122 * McBSP1,3,4,5 has 128 word long buffer
123 * This means that the size of the FIFO depends on the sample format.
124 * For example on McBSP3:
125 * 16bit samples: size is 128 * 2 = 256 bytes
126 * 32bit samples: size is 128 * 4 = 512 bytes
127 * It is simpler to place constraint for buffer and period based on
128 * channels.
129 * McBSP3 as example again (16 or 32 bit samples):
130 * 1 channel (mono): size is 128 frames (128 words)
131 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
132 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
133 */
134 if (mcbsp->pdata->buffer_size) {
135 /*
136 * Rule for the buffer size. We should not allow
137 * smaller buffer than the FIFO size to avoid underruns.
138 * This applies only for the playback stream.
139 */
140 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
141 snd_pcm_hw_rule_add(substream->runtime, 0,
142 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
143 omap_mcbsp_hwrule_min_buffersize,
144 mcbsp,
145 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
146
147 /* Make sure, that the period size is always even */
148 snd_pcm_hw_constraint_step(substream->runtime, 0,
149 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
150 }
151
152 snd_soc_dai_set_dma_data(cpu_dai, substream,
153 &mcbsp->dma_data[substream->stream]);
154
155 return err;
156 }
157
omap_mcbsp_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)158 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
159 struct snd_soc_dai *cpu_dai)
160 {
161 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
162
163 if (!cpu_dai->active) {
164 omap_mcbsp_free(mcbsp);
165 mcbsp->configured = 0;
166 }
167 }
168
omap_mcbsp_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * cpu_dai)169 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
170 struct snd_soc_dai *cpu_dai)
171 {
172 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
173 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
174
175 switch (cmd) {
176 case SNDRV_PCM_TRIGGER_START:
177 case SNDRV_PCM_TRIGGER_RESUME:
178 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
179 mcbsp->active++;
180 omap_mcbsp_start(mcbsp, play, !play);
181 break;
182
183 case SNDRV_PCM_TRIGGER_STOP:
184 case SNDRV_PCM_TRIGGER_SUSPEND:
185 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
186 omap_mcbsp_stop(mcbsp, play, !play);
187 mcbsp->active--;
188 break;
189 default:
190 err = -EINVAL;
191 }
192
193 return err;
194 }
195
omap_mcbsp_dai_delay(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)196 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
197 struct snd_pcm_substream *substream,
198 struct snd_soc_dai *dai)
199 {
200 struct snd_soc_pcm_runtime *rtd = substream->private_data;
201 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
202 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
203 u16 fifo_use;
204 snd_pcm_sframes_t delay;
205
206 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
207 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
208 else
209 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
210
211 /*
212 * Divide the used locations with the channel count to get the
213 * FIFO usage in samples (don't care about partial samples in the
214 * buffer).
215 */
216 delay = fifo_use / substream->runtime->channels;
217
218 return delay;
219 }
220
omap_mcbsp_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)221 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
222 struct snd_pcm_hw_params *params,
223 struct snd_soc_dai *cpu_dai)
224 {
225 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
226 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
227 struct snd_dmaengine_dai_dma_data *dma_data;
228 int wlen, channels, wpf;
229 int pkt_size = 0;
230 unsigned int format, div, framesize, master;
231
232 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
233 channels = params_channels(params);
234
235 switch (params_format(params)) {
236 case SNDRV_PCM_FORMAT_S16_LE:
237 wlen = 16;
238 break;
239 case SNDRV_PCM_FORMAT_S32_LE:
240 wlen = 32;
241 break;
242 default:
243 return -EINVAL;
244 }
245 if (mcbsp->pdata->buffer_size) {
246 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
247 int period_words, max_thrsh;
248 int divider = 0;
249
250 period_words = params_period_bytes(params) / (wlen / 8);
251 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
252 max_thrsh = mcbsp->max_tx_thres;
253 else
254 max_thrsh = mcbsp->max_rx_thres;
255 /*
256 * Use sDMA packet mode if McBSP is in threshold mode:
257 * If period words less than the FIFO size the packet
258 * size is set to the number of period words, otherwise
259 * Look for the biggest threshold value which divides
260 * the period size evenly.
261 */
262 divider = period_words / max_thrsh;
263 if (period_words % max_thrsh)
264 divider++;
265 while (period_words % divider &&
266 divider < period_words)
267 divider++;
268 if (divider == period_words)
269 return -EINVAL;
270
271 pkt_size = period_words / divider;
272 } else if (channels > 1) {
273 /* Use packet mode for non mono streams */
274 pkt_size = channels;
275 }
276 omap_mcbsp_set_threshold(substream, pkt_size);
277 }
278
279 dma_data->maxburst = pkt_size;
280
281 if (mcbsp->configured) {
282 /* McBSP already configured by another stream */
283 return 0;
284 }
285
286 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
287 regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
288 regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
289 regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
290 format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
291 wpf = channels;
292 if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
293 format == SND_SOC_DAIFMT_LEFT_J)) {
294 /* Use dual-phase frames */
295 regs->rcr2 |= RPHASE;
296 regs->xcr2 |= XPHASE;
297 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
298 wpf--;
299 regs->rcr2 |= RFRLEN2(wpf - 1);
300 regs->xcr2 |= XFRLEN2(wpf - 1);
301 }
302
303 regs->rcr1 |= RFRLEN1(wpf - 1);
304 regs->xcr1 |= XFRLEN1(wpf - 1);
305
306 switch (params_format(params)) {
307 case SNDRV_PCM_FORMAT_S16_LE:
308 /* Set word lengths */
309 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
310 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
311 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
312 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
313 break;
314 case SNDRV_PCM_FORMAT_S32_LE:
315 /* Set word lengths */
316 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
317 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
318 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
319 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
320 break;
321 default:
322 /* Unsupported PCM format */
323 return -EINVAL;
324 }
325
326 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
327 * by _counting_ BCLKs. Calculate frame size in BCLKs */
328 master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
329 if (master == SND_SOC_DAIFMT_CBS_CFS) {
330 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
331 framesize = (mcbsp->in_freq / div) / params_rate(params);
332
333 if (framesize < wlen * channels) {
334 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
335 "channels\n", __func__);
336 return -EINVAL;
337 }
338 } else
339 framesize = wlen * channels;
340
341 /* Set FS period and length in terms of bit clock periods */
342 regs->srgr2 &= ~FPER(0xfff);
343 regs->srgr1 &= ~FWID(0xff);
344 switch (format) {
345 case SND_SOC_DAIFMT_I2S:
346 case SND_SOC_DAIFMT_LEFT_J:
347 regs->srgr2 |= FPER(framesize - 1);
348 regs->srgr1 |= FWID((framesize >> 1) - 1);
349 break;
350 case SND_SOC_DAIFMT_DSP_A:
351 case SND_SOC_DAIFMT_DSP_B:
352 regs->srgr2 |= FPER(framesize - 1);
353 regs->srgr1 |= FWID(0);
354 break;
355 }
356
357 omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
358 mcbsp->wlen = wlen;
359 mcbsp->configured = 1;
360
361 return 0;
362 }
363
364 /*
365 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
366 * cache is initialized here
367 */
omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)368 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
369 unsigned int fmt)
370 {
371 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
372 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
373 bool inv_fs = false;
374
375 if (mcbsp->configured)
376 return 0;
377
378 mcbsp->fmt = fmt;
379 memset(regs, 0, sizeof(*regs));
380 /* Generic McBSP register settings */
381 regs->spcr2 |= XINTM(3) | FREE;
382 regs->spcr1 |= RINTM(3);
383 /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
384 if (!mcbsp->pdata->has_ccr) {
385 regs->rcr2 |= RFIG;
386 regs->xcr2 |= XFIG;
387 }
388
389 /* Configure XCCR/RCCR only for revisions which have ccr registers */
390 if (mcbsp->pdata->has_ccr) {
391 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
392 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
393 }
394
395 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
396 case SND_SOC_DAIFMT_I2S:
397 /* 1-bit data delay */
398 regs->rcr2 |= RDATDLY(1);
399 regs->xcr2 |= XDATDLY(1);
400 break;
401 case SND_SOC_DAIFMT_LEFT_J:
402 /* 0-bit data delay */
403 regs->rcr2 |= RDATDLY(0);
404 regs->xcr2 |= XDATDLY(0);
405 regs->spcr1 |= RJUST(2);
406 /* Invert FS polarity configuration */
407 inv_fs = true;
408 break;
409 case SND_SOC_DAIFMT_DSP_A:
410 /* 1-bit data delay */
411 regs->rcr2 |= RDATDLY(1);
412 regs->xcr2 |= XDATDLY(1);
413 /* Invert FS polarity configuration */
414 inv_fs = true;
415 break;
416 case SND_SOC_DAIFMT_DSP_B:
417 /* 0-bit data delay */
418 regs->rcr2 |= RDATDLY(0);
419 regs->xcr2 |= XDATDLY(0);
420 /* Invert FS polarity configuration */
421 inv_fs = true;
422 break;
423 default:
424 /* Unsupported data format */
425 return -EINVAL;
426 }
427
428 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
429 case SND_SOC_DAIFMT_CBS_CFS:
430 /* McBSP master. Set FS and bit clocks as outputs */
431 regs->pcr0 |= FSXM | FSRM |
432 CLKXM | CLKRM;
433 /* Sample rate generator drives the FS */
434 regs->srgr2 |= FSGM;
435 break;
436 case SND_SOC_DAIFMT_CBM_CFM:
437 /* McBSP slave */
438 break;
439 default:
440 /* Unsupported master/slave configuration */
441 return -EINVAL;
442 }
443
444 /* Set bit clock (CLKX/CLKR) and FS polarities */
445 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
446 case SND_SOC_DAIFMT_NB_NF:
447 /*
448 * Normal BCLK + FS.
449 * FS active low. TX data driven on falling edge of bit clock
450 * and RX data sampled on rising edge of bit clock.
451 */
452 regs->pcr0 |= FSXP | FSRP |
453 CLKXP | CLKRP;
454 break;
455 case SND_SOC_DAIFMT_NB_IF:
456 regs->pcr0 |= CLKXP | CLKRP;
457 break;
458 case SND_SOC_DAIFMT_IB_NF:
459 regs->pcr0 |= FSXP | FSRP;
460 break;
461 case SND_SOC_DAIFMT_IB_IF:
462 break;
463 default:
464 return -EINVAL;
465 }
466 if (inv_fs == true)
467 regs->pcr0 ^= FSXP | FSRP;
468
469 return 0;
470 }
471
omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)472 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
473 int div_id, int div)
474 {
475 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
476 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
477
478 if (div_id != OMAP_MCBSP_CLKGDV)
479 return -ENODEV;
480
481 mcbsp->clk_div = div;
482 regs->srgr1 &= ~CLKGDV(0xff);
483 regs->srgr1 |= CLKGDV(div - 1);
484
485 return 0;
486 }
487
omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)488 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
489 int clk_id, unsigned int freq,
490 int dir)
491 {
492 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
493 struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
494 int err = 0;
495
496 if (mcbsp->active) {
497 if (freq == mcbsp->in_freq)
498 return 0;
499 else
500 return -EBUSY;
501 }
502
503 mcbsp->in_freq = freq;
504 regs->srgr2 &= ~CLKSM;
505 regs->pcr0 &= ~SCLKME;
506
507 switch (clk_id) {
508 case OMAP_MCBSP_SYSCLK_CLK:
509 regs->srgr2 |= CLKSM;
510 break;
511 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
512 if (mcbsp_omap1()) {
513 err = -EINVAL;
514 break;
515 }
516 err = omap2_mcbsp_set_clks_src(mcbsp,
517 MCBSP_CLKS_PRCM_SRC);
518 break;
519 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
520 if (mcbsp_omap1()) {
521 err = 0;
522 break;
523 }
524 err = omap2_mcbsp_set_clks_src(mcbsp,
525 MCBSP_CLKS_PAD_SRC);
526 break;
527
528 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
529 regs->srgr2 |= CLKSM;
530 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
531 regs->pcr0 |= SCLKME;
532 break;
533 default:
534 err = -ENODEV;
535 }
536
537 return err;
538 }
539
540 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
541 .startup = omap_mcbsp_dai_startup,
542 .shutdown = omap_mcbsp_dai_shutdown,
543 .trigger = omap_mcbsp_dai_trigger,
544 .delay = omap_mcbsp_dai_delay,
545 .hw_params = omap_mcbsp_dai_hw_params,
546 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
547 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
548 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
549 };
550
omap_mcbsp_probe(struct snd_soc_dai * dai)551 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
552 {
553 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
554
555 pm_runtime_enable(mcbsp->dev);
556
557 return 0;
558 }
559
omap_mcbsp_remove(struct snd_soc_dai * dai)560 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
561 {
562 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
563
564 pm_runtime_disable(mcbsp->dev);
565
566 return 0;
567 }
568
569 static struct snd_soc_dai_driver omap_mcbsp_dai = {
570 .probe = omap_mcbsp_probe,
571 .remove = omap_mcbsp_remove,
572 .playback = {
573 .channels_min = 1,
574 .channels_max = 16,
575 .rates = OMAP_MCBSP_RATES,
576 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
577 },
578 .capture = {
579 .channels_min = 1,
580 .channels_max = 16,
581 .rates = OMAP_MCBSP_RATES,
582 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
583 },
584 .ops = &mcbsp_dai_ops,
585 };
586
587 static const struct snd_soc_component_driver omap_mcbsp_component = {
588 .name = "omap-mcbsp",
589 };
590
omap_mcbsp_st_info_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)591 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
592 struct snd_ctl_elem_info *uinfo)
593 {
594 struct soc_mixer_control *mc =
595 (struct soc_mixer_control *)kcontrol->private_value;
596 int max = mc->max;
597 int min = mc->min;
598
599 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
600 uinfo->count = 1;
601 uinfo->value.integer.min = min;
602 uinfo->value.integer.max = max;
603 return 0;
604 }
605
606 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel) \
607 static int \
608 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
609 struct snd_ctl_elem_value *uc) \
610 { \
611 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
612 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
613 struct soc_mixer_control *mc = \
614 (struct soc_mixer_control *)kc->private_value; \
615 int max = mc->max; \
616 int min = mc->min; \
617 int val = uc->value.integer.value[0]; \
618 \
619 if (val < min || val > max) \
620 return -EINVAL; \
621 \
622 /* OMAP McBSP implementation uses index values 0..4 */ \
623 return omap_st_set_chgain(mcbsp, channel, val); \
624 } \
625 \
626 static int \
627 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
628 struct snd_ctl_elem_value *uc) \
629 { \
630 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc); \
631 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai); \
632 s16 chgain; \
633 \
634 if (omap_st_get_chgain(mcbsp, channel, &chgain)) \
635 return -EAGAIN; \
636 \
637 uc->value.integer.value[0] = chgain; \
638 return 0; \
639 }
640
641 OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
642 OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
643
omap_mcbsp_st_put_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)644 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
645 struct snd_ctl_elem_value *ucontrol)
646 {
647 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
648 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
649 u8 value = ucontrol->value.integer.value[0];
650
651 if (value == omap_st_is_enabled(mcbsp))
652 return 0;
653
654 if (value)
655 omap_st_enable(mcbsp);
656 else
657 omap_st_disable(mcbsp);
658
659 return 1;
660 }
661
omap_mcbsp_st_get_mode(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)662 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
663 struct snd_ctl_elem_value *ucontrol)
664 {
665 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
666 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
667
668 ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
669 return 0;
670 }
671
672 #define OMAP_MCBSP_ST_CONTROLS(port) \
673 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
674 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0, \
675 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), \
676 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
677 -32768, 32767, \
678 omap_mcbsp_get_st_ch0_volume, \
679 omap_mcbsp_set_st_ch0_volume), \
680 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
681 -32768, 32767, \
682 omap_mcbsp_get_st_ch1_volume, \
683 omap_mcbsp_set_st_ch1_volume), \
684 }
685
686 OMAP_MCBSP_ST_CONTROLS(2);
687 OMAP_MCBSP_ST_CONTROLS(3);
688
omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime * rtd)689 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
690 {
691 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
692 struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
693
694 if (!mcbsp->st_data) {
695 dev_warn(mcbsp->dev, "No sidetone data for port\n");
696 return 0;
697 }
698
699 switch (mcbsp->id) {
700 case 2: /* McBSP 2 */
701 return snd_soc_add_dai_controls(cpu_dai,
702 omap_mcbsp2_st_controls,
703 ARRAY_SIZE(omap_mcbsp2_st_controls));
704 case 3: /* McBSP 3 */
705 return snd_soc_add_dai_controls(cpu_dai,
706 omap_mcbsp3_st_controls,
707 ARRAY_SIZE(omap_mcbsp3_st_controls));
708 default:
709 break;
710 }
711
712 return -EINVAL;
713 }
714 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
715
716 static struct omap_mcbsp_platform_data omap2420_pdata = {
717 .reg_step = 4,
718 .reg_size = 2,
719 };
720
721 static struct omap_mcbsp_platform_data omap2430_pdata = {
722 .reg_step = 4,
723 .reg_size = 4,
724 .has_ccr = true,
725 };
726
727 static struct omap_mcbsp_platform_data omap3_pdata = {
728 .reg_step = 4,
729 .reg_size = 4,
730 .has_ccr = true,
731 .has_wakeup = true,
732 };
733
734 static struct omap_mcbsp_platform_data omap4_pdata = {
735 .reg_step = 4,
736 .reg_size = 4,
737 .has_ccr = true,
738 .has_wakeup = true,
739 };
740
741 static const struct of_device_id omap_mcbsp_of_match[] = {
742 {
743 .compatible = "ti,omap2420-mcbsp",
744 .data = &omap2420_pdata,
745 },
746 {
747 .compatible = "ti,omap2430-mcbsp",
748 .data = &omap2430_pdata,
749 },
750 {
751 .compatible = "ti,omap3-mcbsp",
752 .data = &omap3_pdata,
753 },
754 {
755 .compatible = "ti,omap4-mcbsp",
756 .data = &omap4_pdata,
757 },
758 { },
759 };
760 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
761
asoc_mcbsp_probe(struct platform_device * pdev)762 static int asoc_mcbsp_probe(struct platform_device *pdev)
763 {
764 struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
765 struct omap_mcbsp *mcbsp;
766 const struct of_device_id *match;
767 int ret;
768
769 match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
770 if (match) {
771 struct device_node *node = pdev->dev.of_node;
772 int buffer_size;
773
774 pdata = devm_kzalloc(&pdev->dev,
775 sizeof(struct omap_mcbsp_platform_data),
776 GFP_KERNEL);
777 if (!pdata)
778 return -ENOMEM;
779
780 memcpy(pdata, match->data, sizeof(*pdata));
781 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
782 pdata->buffer_size = buffer_size;
783 } else if (!pdata) {
784 dev_err(&pdev->dev, "missing platform data.\n");
785 return -EINVAL;
786 }
787 mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
788 if (!mcbsp)
789 return -ENOMEM;
790
791 mcbsp->id = pdev->id;
792 mcbsp->pdata = pdata;
793 mcbsp->dev = &pdev->dev;
794 platform_set_drvdata(pdev, mcbsp);
795
796 ret = omap_mcbsp_init(pdev);
797 if (!ret)
798 return snd_soc_register_component(&pdev->dev, &omap_mcbsp_component,
799 &omap_mcbsp_dai, 1);
800
801 return ret;
802 }
803
asoc_mcbsp_remove(struct platform_device * pdev)804 static int asoc_mcbsp_remove(struct platform_device *pdev)
805 {
806 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
807
808 snd_soc_unregister_component(&pdev->dev);
809
810 if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
811 mcbsp->pdata->ops->free(mcbsp->id);
812
813 omap_mcbsp_sysfs_remove(mcbsp);
814
815 clk_put(mcbsp->fclk);
816
817 platform_set_drvdata(pdev, NULL);
818
819 return 0;
820 }
821
822 static struct platform_driver asoc_mcbsp_driver = {
823 .driver = {
824 .name = "omap-mcbsp",
825 .owner = THIS_MODULE,
826 .of_match_table = omap_mcbsp_of_match,
827 },
828
829 .probe = asoc_mcbsp_probe,
830 .remove = asoc_mcbsp_remove,
831 };
832
833 module_platform_driver(asoc_mcbsp_driver);
834
835 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
836 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
837 MODULE_LICENSE("GPL");
838 MODULE_ALIAS("platform:omap-mcbsp");
839