Lines Matching refs:clks
73 clocks = <&clks IMX27_CLK_CPU_DIV>;
96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
97 <&clks IMX27_CLK_DMA_AHB_GATE>;
107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
115 <&clks IMX27_CLK_PER1_GATE>;
123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
124 <&clks IMX27_CLK_PER1_GATE>;
132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
133 <&clks IMX27_CLK_PER1_GATE>;
142 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
143 <&clks IMX27_CLK_PER1_GATE>;
151 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
158 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
166 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
167 <&clks IMX27_CLK_PER1_GATE>;
176 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
177 <&clks IMX27_CLK_PER1_GATE>;
186 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
187 <&clks IMX27_CLK_PER1_GATE>;
196 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
197 <&clks IMX27_CLK_PER1_GATE>;
208 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
209 <&clks IMX27_CLK_PER2_GATE>;
220 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
221 <&clks IMX27_CLK_PER2_GATE>;
231 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
243 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
256 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
264 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
265 <&clks IMX27_CLK_PER2_GATE>;
276 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
277 <&clks IMX27_CLK_PER2_GATE>;
294 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
305 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
316 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
327 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
338 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
349 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
361 clocks = <&clks IMX27_CLK_DUMMY>;
372 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
373 <&clks IMX27_CLK_PER2_GATE>;
382 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
383 <&clks IMX27_CLK_PER1_GATE>;
391 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
392 <&clks IMX27_CLK_PER1_GATE>;
400 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
401 <&clks IMX27_CLK_PER1_GATE>;
410 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
411 <&clks IMX27_CLK_PER1_GATE>;
422 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
430 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
431 <&clks IMX27_CLK_PER2_GATE>;
442 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
443 <&clks IMX27_CLK_PER1_GATE>;
459 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
460 <&clks IMX27_CLK_LCDC_AHB_GATE>,
461 <&clks IMX27_CLK_PER3_GATE>;
470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
471 <&clks IMX27_CLK_VPU_AHB_GATE>;
480 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
489 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
498 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
507 clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
514 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
515 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
519 clks: ccm@10027000{ label
529 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
536 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
537 <&clks IMX27_CLK_FEC_AHB_GATE>;
549 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
558 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;