Lines Matching refs:clks
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
104 clocks = <&clks IMX6SL_CLK_OCRAM>;
147 clocks = <&clks IMX6SL_CLK_ECSPI1>,
148 <&clks IMX6SL_CLK_ECSPI1>;
159 clocks = <&clks IMX6SL_CLK_ECSPI2>,
160 <&clks IMX6SL_CLK_ECSPI2>;
171 clocks = <&clks IMX6SL_CLK_ECSPI3>,
172 <&clks IMX6SL_CLK_ECSPI3>;
183 clocks = <&clks IMX6SL_CLK_ECSPI4>,
184 <&clks IMX6SL_CLK_ECSPI4>;
194 clocks = <&clks IMX6SL_CLK_UART>,
195 <&clks IMX6SL_CLK_UART_SERIAL>;
207 clocks = <&clks IMX6SL_CLK_UART>,
208 <&clks IMX6SL_CLK_UART_SERIAL>;
220 clocks = <&clks IMX6SL_CLK_UART>,
221 <&clks IMX6SL_CLK_UART_SERIAL>;
234 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
235 <&clks IMX6SL_CLK_SSI1>;
250 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
251 <&clks IMX6SL_CLK_SSI2>;
266 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
267 <&clks IMX6SL_CLK_SSI3>;
281 clocks = <&clks IMX6SL_CLK_UART>,
282 <&clks IMX6SL_CLK_UART_SERIAL>;
294 clocks = <&clks IMX6SL_CLK_UART>,
295 <&clks IMX6SL_CLK_UART_SERIAL>;
308 clocks = <&clks IMX6SL_CLK_PWM1>,
309 <&clks IMX6SL_CLK_PWM1>;
318 clocks = <&clks IMX6SL_CLK_PWM2>,
319 <&clks IMX6SL_CLK_PWM2>;
328 clocks = <&clks IMX6SL_CLK_PWM3>,
329 <&clks IMX6SL_CLK_PWM3>;
338 clocks = <&clks IMX6SL_CLK_PWM4>,
339 <&clks IMX6SL_CLK_PWM4>;
347 clocks = <&clks IMX6SL_CLK_GPT>,
348 <&clks IMX6SL_CLK_GPT_SERIAL>;
411 clocks = <&clks IMX6SL_CLK_DUMMY>;
419 clocks = <&clks IMX6SL_CLK_DUMMY>;
426 clocks = <&clks IMX6SL_CLK_DUMMY>;
430 clks: ccm@020c4000 { label
546 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
553 clocks = <&clks IMX6SL_CLK_USBPHY1>;
561 clocks = <&clks IMX6SL_CLK_USBPHY2>;
628 clocks = <&clks IMX6SL_CLK_SDMA>,
629 <&clks IMX6SL_CLK_SDMA>;
650 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
651 <&clks IMX6SL_CLK_LCDIF_AXI>,
652 <&clks IMX6SL_CLK_DUMMY>;
674 clocks = <&clks IMX6SL_CLK_USBOH3>;
684 clocks = <&clks IMX6SL_CLK_USBOH3>;
694 clocks = <&clks IMX6SL_CLK_USBOH3>;
703 clocks = <&clks IMX6SL_CLK_USBOH3>;
710 clocks = <&clks IMX6SL_CLK_ENET>,
711 <&clks IMX6SL_CLK_ENET_REF>;
720 clocks = <&clks IMX6SL_CLK_USDHC1>,
721 <&clks IMX6SL_CLK_USDHC1>,
722 <&clks IMX6SL_CLK_USDHC1>;
732 clocks = <&clks IMX6SL_CLK_USDHC2>,
733 <&clks IMX6SL_CLK_USDHC2>,
734 <&clks IMX6SL_CLK_USDHC2>;
744 clocks = <&clks IMX6SL_CLK_USDHC3>,
745 <&clks IMX6SL_CLK_USDHC3>,
746 <&clks IMX6SL_CLK_USDHC3>;
756 clocks = <&clks IMX6SL_CLK_USDHC4>,
757 <&clks IMX6SL_CLK_USDHC4>,
758 <&clks IMX6SL_CLK_USDHC4>;
770 clocks = <&clks IMX6SL_CLK_I2C1>;
780 clocks = <&clks IMX6SL_CLK_I2C2>;
790 clocks = <&clks IMX6SL_CLK_I2C3>;