107 	writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);  in cns3xxx_power_off()
126 		writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);  in cns3xxx_timer_set_mode()
139 	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);  in cns3xxx_timer_set_mode()
147 	writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);  in cns3xxx_timer_set_next_event()
148 	writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);  in cns3xxx_timer_set_next_event()
181 	writel(val & ~(1 << 2), stat);  in cns3xxx_timer_interrupt()
207 	writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);  in __cns3xxx_timer_init()
209 	writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);  in __cns3xxx_timer_init()
212 	writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);  in __cns3xxx_timer_init()
213 	writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);  in __cns3xxx_timer_init()
215 	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);  in __cns3xxx_timer_init()
216 	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);  in __cns3xxx_timer_init()
222 	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);  in __cns3xxx_timer_init()
227 	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);  in __cns3xxx_timer_init()
230 	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);  in __cns3xxx_timer_init()
231 	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);  in __cns3xxx_timer_init()
236 	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);  in __cns3xxx_timer_init()
241 	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);  in __cns3xxx_timer_init()
277 	writel(val, base + L310_TAG_LATENCY_CTRL);  in cns3xxx_l2x0_init()
290 	writel(val, base + L310_DATA_LATENCY_CTRL);  in cns3xxx_l2x0_init()