217 	__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));  in lpc32xx_mask_irq()
227 	__raw_writel(reg, LPC32XX_INTC_MASK(ctrl));  in lpc32xx_unmask_irq()
236 	__raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));  in lpc32xx_ack_irq()
240 		__raw_writel(lpc32xx_events[d->hwirq].mask,  in lpc32xx_ack_irq()
257 	__raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));  in __lpc32xx_set_irq_type()
265 	__raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));  in __lpc32xx_set_irq_type()
276 		__raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);  in __lpc32xx_set_irq_type()
332 			__raw_writel(lpc32xx_events[d->hwirq].mask,  in lpc32xx_irq_wake()
337 		__raw_writel(eventreg,  in lpc32xx_irq_wake()
344 	__raw_writel(lpc32xx_events[d->hwirq].mask,  in lpc32xx_irq_wake()
417 	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));  in lpc32xx_init_irq()
418 	__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));  in lpc32xx_init_irq()
419 	__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));  in lpc32xx_init_irq()
422 	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));  in lpc32xx_init_irq()
423 	__raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));  in lpc32xx_init_irq()
424 	__raw_writel(SIC1_ATR_DEFAULT,  in lpc32xx_init_irq()
428 	__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));  in lpc32xx_init_irq()
429 	__raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));  in lpc32xx_init_irq()
430 	__raw_writel(SIC2_ATR_DEFAULT,  in lpc32xx_init_irq()
446 	__raw_writel(0, LPC32XX_CLKPWR_P01_ER);  in lpc32xx_init_irq()
447 	__raw_writel(0, LPC32XX_CLKPWR_INT_ER);  in lpc32xx_init_irq()
448 	__raw_writel(0, LPC32XX_CLKPWR_PIN_ER);  in lpc32xx_init_irq()
454 	__raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |  in lpc32xx_init_irq()
458 	__raw_writel(0, LPC32XX_CLKPWR_PIN_AP);  in lpc32xx_init_irq()
461 	__raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),  in lpc32xx_init_irq()
463 	__raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),  in lpc32xx_init_irq()