232 	u16 regval;  in omap1_clk_set_rate_dsp_domain()  local
240 	regval = __raw_readw(DSP_CKCTL);  in omap1_clk_set_rate_dsp_domain()
241 	regval &= ~(3 << clk->rate_offset);  in omap1_clk_set_rate_dsp_domain()
242 	regval |= dsor_exp << clk->rate_offset;  in omap1_clk_set_rate_dsp_domain()
243 	__raw_writew(regval, DSP_CKCTL);  in omap1_clk_set_rate_dsp_domain()
262 	u16 regval;  in omap1_clk_set_rate_ckctl_arm()  local
270 	regval = omap_readw(ARM_CKCTL);  in omap1_clk_set_rate_ckctl_arm()
271 	regval &= ~(3 << clk->rate_offset);  in omap1_clk_set_rate_ckctl_arm()
272 	regval |= dsor_exp << clk->rate_offset;  in omap1_clk_set_rate_ckctl_arm()
273 	regval = verify_ckctl_value(regval);  in omap1_clk_set_rate_ckctl_arm()
274 	omap_writew(regval, ARM_CKCTL);  in omap1_clk_set_rate_ckctl_arm()