Lines Matching defs:gpmc_device_timings

141 struct gpmc_device_timings {  struct
142 	u32 t_ceasu;	/* address setup to CS valid */
143 	u32 t_avdasu;	/* address setup to ADV valid */
151 	u32 t_avdp_r;	/* ADV low time (what about t_cer ?) */
152 	u32 t_avdp_w;
153 	u32 t_aavdh;	/* address hold time */
154 	u32 t_oeasu;	/* address setup to OE valid */
155 	u32 t_aa;	/* access time from ADV assertion */
156 	u32 t_iaa;	/* initial access time */
157 	u32 t_oe;	/* access time from OE assertion */
158 	u32 t_ce;	/* access time from CS asertion */
159 	u32 t_rd_cycle;	/* read cycle time */
160 	u32 t_cez_r;	/* read CS deassertion to high Z */
161 	u32 t_cez_w;	/* write CS deassertion to high Z */
162 	u32 t_oez;	/* OE deassertion to high Z */
163 	u32 t_weasu;	/* address setup to WE valid */
164 	u32 t_wpl;	/* write assertion time */
165 	u32 t_wph;	/* write deassertion time */
166 	u32 t_wr_cycle;	/* write cycle time */
168 	u32 clk;
169 	u32 t_bacc;	/* burst access valid clock to output delay */
170 	u32 t_ces;	/* CS setup time to clk */
171 	u32 t_avds;	/* ADV setup time to clk */
172 	u32 t_avdh;	/* ADV hold time from clk */
173 	u32 t_ach;	/* address hold time from clk */
174 	u32 t_rdyo;	/* clk to ready valid */
176 	u32 t_ce_rdyz;	/* XXX: description ?, or use t_cez instead */
177 	u32 t_ce_avd;	/* CS on to ADV on delay */
182 	u8 cyc_aavdh_oe;/* read address hold time in cycles */
183 	u8 cyc_aavdh_we;/* write address hold time in cycles */
184 	u8 cyc_oe;	/* access time from OE assertion in cycles */
185 	u8 cyc_wpl;	/* write deassertion time in cycles */
186 	u32 cyc_iaa;	/* initial access time in cycles */
212 			     struct gpmc_device_timings *dev_t);  argument