Lines Matching refs:r12
122 stmfd sp!, {r1-r12, lr} @ store regs to stack
169 mov r12, r2
182 ldmfd sp!, {r1-r12, pc} @ restore regs and return
185 ldr r12, [r11]
186 bic r12, r12, #FIXEDDELAY_MASK
187 orr r12, r12, #FIXEDDELAY_DEFAULT
188 orr r12, r12, #DLLIDLE_MASK
189 str r12, [r11] @ (no OCP barrier needed)
193 ldr r12, [r11]
194 bic r12, r12, #DLLIDLE_MASK
195 str r12, [r11] @ (no OCP barrier needed)
199 ldr r12, [r11] @ read the contents of SDRC_POWER
200 mov r9, r12 @ keep a copy of SDRC_POWER bits
201 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
202 str r12, [r11] @ write back to SDRC_POWER register
203 ldr r12, [r11] @ posted-write barrier for SDRC
206 ldr r12, [r11]
207 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
208 str r12, [r11]
211 ldr r12, [r11]
212 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
213 cmp r12, #ST_SDRC_MASK
218 ldr r12, [r11]
220 and r12, r12, r10
221 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
222 str r12, [r11]
223 ldr r12, [r11] @ posted-write barrier for CM
226 subs r12, r12, #1
231 ldr r12, [r11]
232 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
233 str r12, [r11]
236 ldr r12, [r11]
237 and r12, r12, #ST_SDRC_MASK
238 cmp r12, #0
246 ldr r12, [r11]
247 and r12, r12, #LOCKSTATUS_MASK
248 cmp r12, #LOCKSTATUS_MASK
253 ldr r12, [r11]
254 and r12, r12, #LOCKSTATUS_MASK
255 cmp r12, #0x0
259 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
261 str r12, [r11] @ store
263 ldr r12, omap_sdrc_actim_ctrl_a_0_val
265 str r12, [r11]
266 ldr r12, omap_sdrc_actim_ctrl_b_0_val
268 str r12, [r11]
269 ldr r12, omap_sdrc_mr_0_val
271 str r12, [r11]
273 ldr r12, omap_sdrc_rfr_ctrl_1_val
274 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
277 str r12, [r11]
279 ldr r12, omap_sdrc_actim_ctrl_a_1_val
281 str r12, [r11]
282 ldr r12, omap_sdrc_actim_ctrl_b_1_val
284 str r12, [r11]
285 ldr r12, omap_sdrc_mr_1_val
287 str r12, [r11]
290 ldr r12, [r11] @ posted-write barrier for SDRC