Lines Matching refs:pll1_clk
101 SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
103 SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
109 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
110 SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
111 SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
112 SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
114 SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
115 SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
116 SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
122 &pll1_clk,
154 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
155 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
232 CLKDEV_CON_ID("pll1", &pll1_clk),