Lines Matching refs:r0
41 mrc p15, 0, r0, c1, c0, 0
42 bic r0, r0, #0x3f000000 @ bank/f/lock/s
43 bic r0, r0, #0x0000000c @ w-buffer/cache
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 ret r0
65 mov r0, #0
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
68 mcr p15, 0, r0, c6, c3 @ disable area 3~7
69 mcr p15, 0, r0, c6, c4
70 mcr p15, 0, r0, c6, c5
71 mcr p15, 0, r0, c6, c6
72 mcr p15, 0, r0, c6, c7
74 mov r0, #0x0000003F @ base = 0, size = 4GB
75 mcr p15, 0, r0, c6, c0 @ set area 0, default
77 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
83 orr r0, r0, r4, lsl #1 @ the area register value
84 orr r0, r0, #1 @ set enable bit
85 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
87 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
90 moveq r0, #0
96 orr r0, r0, r4, lsl #1 @ the area register value
97 orr r0, r0, #1 @ set enable bit
98 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
100 mov r0, #0x06
101 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
103 mov r0, #0x00 @ disable whole write buffer
105 mov r0, #0x02 @ Region 1 write bufferred
107 mcr p15, 0, r0, c3, c0
109 mov r0, #0x10000
110 sub r0, r0, #1 @ r0 = 0xffff
111 mcr p15, 0, r0, c5, c0 @ all read/write access
113 mrc p15, 0, r0, c1, c0 @ get control register
114 bic r0, r0, #0x3F000000 @ set to standard caching mode
116 orr r0, r0, #0x0000000d @ MPU/Cache/WB