Lines Matching refs:r0
95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
132 ret r0
141 mov r0, #0
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
156 mov r0, #0
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
205 sub r3, r1, r0 @ calculate total size
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 add r0, r0, #CACHE_DLINESIZE
213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
215 add r0, r0, #CACHE_DLINESIZE
217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 add r0, r0, #CACHE_DLINESIZE
220 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
221 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 add r0, r0, #CACHE_DLINESIZE
224 cmp r0, r1
254 bic r0, r0, #CACHE_DLINESIZE - 1
255 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
257 add r0, r0, #CACHE_DLINESIZE
258 cmp r0, r1
260 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 mov r0, #0
274 add r1, r0, r1
275 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
276 add r0, r0, #CACHE_DLINESIZE
277 cmp r0, r1
279 mov r0, #0
280 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
299 tst r0, #CACHE_DLINESIZE - 1
300 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
304 bic r0, r0, #CACHE_DLINESIZE - 1
305 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
306 add r0, r0, #CACHE_DLINESIZE
307 cmp r0, r1
309 mcr p15, 0, r0, c7, c10, 4 @ drain WB
324 bic r0, r0, #CACHE_DLINESIZE - 1
325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 add r0, r0, #CACHE_DLINESIZE
327 cmp r0, r1
330 mcr p15, 0, r0, c7, c10, 4 @ drain WB
342 bic r0, r0, #CACHE_DLINESIZE - 1
345 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
347 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
349 add r0, r0, #CACHE_DLINESIZE
350 cmp r0, r1
352 mcr p15, 0, r0, c7, c10, 4 @ drain WB
362 add r1, r1, r0
387 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
388 add r0, r0, #CACHE_DLINESIZE
392 mcr p15, 0, r0, c7, c10, 4 @ drain WB
419 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
433 mov r0, r0
435 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
437 mcr p15, 0, r0, c7, c10, 4 @ drain WB
443 mov r0, #0
445 orr r0,r0,#1 << 7
449 orr r0,r0,#1 << 1 @ transparent mode on
450 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
452 mov r0, #0
453 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
454 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
456 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
460 mov r0, #4 @ disable write-back on caches explicitly
461 mcr p15, 7, r0, c15, c0, 0
466 mrc p15, 0, r0, c1, c0 @ get control register v4
467 bic r0, r0, r5
468 orr r0, r0, r6
470 orr r0, r0, #0x4000 @ .1.. .... .... ....