Lines Matching refs:r0
47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
48 bic r0, r0, #0x00001000 @ i-cache
49 bic r0, r0, #0x00000004 @ d-cache
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 ret r0
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
86 mov r0, #0
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 sub r3, r1, r0 @ calculate total size
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 add r0, r0, #CACHE_DLINESIZE
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
146 add r0, r0, #CACHE_DLINESIZE
148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
150 add r0, r0, #CACHE_DLINESIZE
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
153 add r0, r0, #CACHE_DLINESIZE
155 cmp r0, r1
186 bic r0, r0, #CACHE_DLINESIZE - 1
187 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
189 add r0, r0, #CACHE_DLINESIZE
190 cmp r0, r1
192 mcr p15, 0, r0, c7, c10, 4 @ drain WB
193 mov r0, #0
207 add r1, r0, r1
208 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
209 add r0, r0, #CACHE_DLINESIZE
210 cmp r0, r1
212 mov r0, #0
213 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
214 mcr p15, 0, r0, c7, c10, 4 @ drain WB
231 tst r0, #CACHE_DLINESIZE - 1
232 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
236 bic r0, r0, #CACHE_DLINESIZE - 1
237 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
238 add r0, r0, #CACHE_DLINESIZE
239 cmp r0, r1
241 mcr p15, 0, r0, c7, c10, 4 @ drain WB
256 bic r0, r0, #CACHE_DLINESIZE - 1
257 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
258 add r0, r0, #CACHE_DLINESIZE
259 cmp r0, r1
262 mcr p15, 0, r0, c7, c10, 4 @ drain WB
276 bic r0, r0, #CACHE_DLINESIZE - 1
279 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
281 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
283 add r0, r0, #CACHE_DLINESIZE
284 cmp r0, r1
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
296 add r1, r1, r0
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
322 add r0, r0, #CACHE_DLINESIZE
326 mcr p15, 0, r0, c7, c10, 4 @ drain WB
331 mov r0, #0
332 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
333 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
334 mcr p15, 0, r0, c7, c10, 4 @ drain WB
336 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
337 mcr p15, 0, r0, c6, c4, 0
338 mcr p15, 0, r0, c6, c5, 0
339 mcr p15, 0, r0, c6, c6, 0
340 mcr p15, 0, r0, c6, c7, 0
342 mov r0, #0x0000003F @ base = 0, size = 4GB
343 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
345 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
351 orr r0, r0, r2, lsl #1 @ the region register value
352 orr r0, r0, #1 @ set enable bit
353 mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
355 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
361 orr r0, r0, r2, lsl #1 @ the region register value
362 orr r0, r0, #1 @ set enable bit
363 mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
365 mov r0, #0x06
366 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
367 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
369 mov r0, #0x00 @ disable whole write buffer
371 mov r0, #0x02 @ region 1 write bufferred
373 mcr p15, 0, r0, c3, c0, 0
384 mov r0, #0x00000031
385 orr r0, r0, #0x00000200
386 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
387 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
389 mrc p15, 0, r0, c1, c0 @ get control register
390 orr r0, r0, #0x00001000 @ I-cache
391 orr r0, r0, #0x00000005 @ MPU/D-cache
393 orr r0, r0, #0x00004000 @ .1.. .... .... ....