Lines Matching refs:D32
38 #define D32(name) d(#name, 32, name) macro
603 D32(TCNTL); in bfin_debug_mmrs_init()
604 D32(TCOUNT); in bfin_debug_mmrs_init()
605 D32(TPERIOD); in bfin_debug_mmrs_init()
606 D32(TSCALE); in bfin_debug_mmrs_init()
609 D32(EVT0); in bfin_debug_mmrs_init()
610 D32(EVT1); in bfin_debug_mmrs_init()
611 D32(EVT2); in bfin_debug_mmrs_init()
612 D32(EVT3); in bfin_debug_mmrs_init()
613 D32(EVT4); in bfin_debug_mmrs_init()
614 D32(EVT5); in bfin_debug_mmrs_init()
615 D32(EVT6); in bfin_debug_mmrs_init()
616 D32(EVT7); in bfin_debug_mmrs_init()
617 D32(EVT8); in bfin_debug_mmrs_init()
618 D32(EVT9); in bfin_debug_mmrs_init()
619 D32(EVT10); in bfin_debug_mmrs_init()
620 D32(EVT11); in bfin_debug_mmrs_init()
621 D32(EVT12); in bfin_debug_mmrs_init()
622 D32(EVT13); in bfin_debug_mmrs_init()
623 D32(EVT14); in bfin_debug_mmrs_init()
624 D32(EVT15); in bfin_debug_mmrs_init()
625 D32(EVT_OVERRIDE); in bfin_debug_mmrs_init()
626 D32(IMASK); in bfin_debug_mmrs_init()
627 D32(IPEND); in bfin_debug_mmrs_init()
628 D32(ILAT); in bfin_debug_mmrs_init()
629 D32(IPRIO); in bfin_debug_mmrs_init()
632 D32(DBGSTAT); in bfin_debug_mmrs_init()
633 D32(DSPID); in bfin_debug_mmrs_init()
636 D32(SRAM_BASE_ADDRESS); in bfin_debug_mmrs_init()
637 D32(DCPLB_ADDR0); in bfin_debug_mmrs_init()
638 D32(DCPLB_ADDR10); in bfin_debug_mmrs_init()
639 D32(DCPLB_ADDR11); in bfin_debug_mmrs_init()
640 D32(DCPLB_ADDR12); in bfin_debug_mmrs_init()
641 D32(DCPLB_ADDR13); in bfin_debug_mmrs_init()
642 D32(DCPLB_ADDR14); in bfin_debug_mmrs_init()
643 D32(DCPLB_ADDR15); in bfin_debug_mmrs_init()
644 D32(DCPLB_ADDR1); in bfin_debug_mmrs_init()
645 D32(DCPLB_ADDR2); in bfin_debug_mmrs_init()
646 D32(DCPLB_ADDR3); in bfin_debug_mmrs_init()
647 D32(DCPLB_ADDR4); in bfin_debug_mmrs_init()
648 D32(DCPLB_ADDR5); in bfin_debug_mmrs_init()
649 D32(DCPLB_ADDR6); in bfin_debug_mmrs_init()
650 D32(DCPLB_ADDR7); in bfin_debug_mmrs_init()
651 D32(DCPLB_ADDR8); in bfin_debug_mmrs_init()
652 D32(DCPLB_ADDR9); in bfin_debug_mmrs_init()
653 D32(DCPLB_DATA0); in bfin_debug_mmrs_init()
654 D32(DCPLB_DATA10); in bfin_debug_mmrs_init()
655 D32(DCPLB_DATA11); in bfin_debug_mmrs_init()
656 D32(DCPLB_DATA12); in bfin_debug_mmrs_init()
657 D32(DCPLB_DATA13); in bfin_debug_mmrs_init()
658 D32(DCPLB_DATA14); in bfin_debug_mmrs_init()
659 D32(DCPLB_DATA15); in bfin_debug_mmrs_init()
660 D32(DCPLB_DATA1); in bfin_debug_mmrs_init()
661 D32(DCPLB_DATA2); in bfin_debug_mmrs_init()
662 D32(DCPLB_DATA3); in bfin_debug_mmrs_init()
663 D32(DCPLB_DATA4); in bfin_debug_mmrs_init()
664 D32(DCPLB_DATA5); in bfin_debug_mmrs_init()
665 D32(DCPLB_DATA6); in bfin_debug_mmrs_init()
666 D32(DCPLB_DATA7); in bfin_debug_mmrs_init()
667 D32(DCPLB_DATA8); in bfin_debug_mmrs_init()
668 D32(DCPLB_DATA9); in bfin_debug_mmrs_init()
669 D32(DCPLB_FAULT_ADDR); in bfin_debug_mmrs_init()
670 D32(DCPLB_STATUS); in bfin_debug_mmrs_init()
671 D32(DMEM_CONTROL); in bfin_debug_mmrs_init()
672 D32(DTEST_COMMAND); in bfin_debug_mmrs_init()
673 D32(DTEST_DATA0); in bfin_debug_mmrs_init()
674 D32(DTEST_DATA1); in bfin_debug_mmrs_init()
676 D32(ICPLB_ADDR0); in bfin_debug_mmrs_init()
677 D32(ICPLB_ADDR1); in bfin_debug_mmrs_init()
678 D32(ICPLB_ADDR2); in bfin_debug_mmrs_init()
679 D32(ICPLB_ADDR3); in bfin_debug_mmrs_init()
680 D32(ICPLB_ADDR4); in bfin_debug_mmrs_init()
681 D32(ICPLB_ADDR5); in bfin_debug_mmrs_init()
682 D32(ICPLB_ADDR6); in bfin_debug_mmrs_init()
683 D32(ICPLB_ADDR7); in bfin_debug_mmrs_init()
684 D32(ICPLB_ADDR8); in bfin_debug_mmrs_init()
685 D32(ICPLB_ADDR9); in bfin_debug_mmrs_init()
686 D32(ICPLB_ADDR10); in bfin_debug_mmrs_init()
687 D32(ICPLB_ADDR11); in bfin_debug_mmrs_init()
688 D32(ICPLB_ADDR12); in bfin_debug_mmrs_init()
689 D32(ICPLB_ADDR13); in bfin_debug_mmrs_init()
690 D32(ICPLB_ADDR14); in bfin_debug_mmrs_init()
691 D32(ICPLB_ADDR15); in bfin_debug_mmrs_init()
692 D32(ICPLB_DATA0); in bfin_debug_mmrs_init()
693 D32(ICPLB_DATA1); in bfin_debug_mmrs_init()
694 D32(ICPLB_DATA2); in bfin_debug_mmrs_init()
695 D32(ICPLB_DATA3); in bfin_debug_mmrs_init()
696 D32(ICPLB_DATA4); in bfin_debug_mmrs_init()
697 D32(ICPLB_DATA5); in bfin_debug_mmrs_init()
698 D32(ICPLB_DATA6); in bfin_debug_mmrs_init()
699 D32(ICPLB_DATA7); in bfin_debug_mmrs_init()
700 D32(ICPLB_DATA8); in bfin_debug_mmrs_init()
701 D32(ICPLB_DATA9); in bfin_debug_mmrs_init()
702 D32(ICPLB_DATA10); in bfin_debug_mmrs_init()
703 D32(ICPLB_DATA11); in bfin_debug_mmrs_init()
704 D32(ICPLB_DATA12); in bfin_debug_mmrs_init()
705 D32(ICPLB_DATA13); in bfin_debug_mmrs_init()
706 D32(ICPLB_DATA14); in bfin_debug_mmrs_init()
707 D32(ICPLB_DATA15); in bfin_debug_mmrs_init()
708 D32(ICPLB_FAULT_ADDR); in bfin_debug_mmrs_init()
709 D32(ICPLB_STATUS); in bfin_debug_mmrs_init()
710 D32(IMEM_CONTROL); in bfin_debug_mmrs_init()
712 D32(ITEST_COMMAND); in bfin_debug_mmrs_init()
713 D32(ITEST_DATA0); in bfin_debug_mmrs_init()
714 D32(ITEST_DATA1); in bfin_debug_mmrs_init()
718 D32(PFCNTR0); in bfin_debug_mmrs_init()
719 D32(PFCNTR1); in bfin_debug_mmrs_init()
720 D32(PFCTL); in bfin_debug_mmrs_init()
723 D32(TBUF); in bfin_debug_mmrs_init()
724 D32(TBUFCTL); in bfin_debug_mmrs_init()
725 D32(TBUFSTAT); in bfin_debug_mmrs_init()
728 D32(WPIACTL); in bfin_debug_mmrs_init()
729 D32(WPIA0); in bfin_debug_mmrs_init()
730 D32(WPIA1); in bfin_debug_mmrs_init()
731 D32(WPIA2); in bfin_debug_mmrs_init()
732 D32(WPIA3); in bfin_debug_mmrs_init()
733 D32(WPIA4); in bfin_debug_mmrs_init()
734 D32(WPIA5); in bfin_debug_mmrs_init()
735 D32(WPIACNT0); in bfin_debug_mmrs_init()
736 D32(WPIACNT1); in bfin_debug_mmrs_init()
737 D32(WPIACNT2); in bfin_debug_mmrs_init()
738 D32(WPIACNT3); in bfin_debug_mmrs_init()
739 D32(WPIACNT4); in bfin_debug_mmrs_init()
740 D32(WPIACNT5); in bfin_debug_mmrs_init()
741 D32(WPDACTL); in bfin_debug_mmrs_init()
742 D32(WPDA0); in bfin_debug_mmrs_init()
743 D32(WPDA1); in bfin_debug_mmrs_init()
744 D32(WPDACNT0); in bfin_debug_mmrs_init()
745 D32(WPDACNT1); in bfin_debug_mmrs_init()
746 D32(WPSTAT); in bfin_debug_mmrs_init()
795 D32(CNT_COUNTER); in bfin_debug_mmrs_init()
798 D32(CNT_MAX); in bfin_debug_mmrs_init()
799 D32(CNT_MIN); in bfin_debug_mmrs_init()
881 D32(EBIU_AMBCTL0); in bfin_debug_mmrs_init()
882 D32(EBIU_AMBCTL1); in bfin_debug_mmrs_init()
886 D32(EBIU_ARBSTAT); in bfin_debug_mmrs_init()
887 D32(EBIU_MODE); in bfin_debug_mmrs_init()
894 D32(EBIU_SDBCTL); in bfin_debug_mmrs_init()
898 D32(EBIU_SDGCTL); in bfin_debug_mmrs_init()
905 D32(EBIU_DDRACCT); in bfin_debug_mmrs_init()
906 D32(EBIU_DDRARCT); in bfin_debug_mmrs_init()
907 D32(EBIU_DDRBRC0); in bfin_debug_mmrs_init()
908 D32(EBIU_DDRBRC1); in bfin_debug_mmrs_init()
909 D32(EBIU_DDRBRC2); in bfin_debug_mmrs_init()
910 D32(EBIU_DDRBRC3); in bfin_debug_mmrs_init()
911 D32(EBIU_DDRBRC4); in bfin_debug_mmrs_init()
912 D32(EBIU_DDRBRC5); in bfin_debug_mmrs_init()
913 D32(EBIU_DDRBRC6); in bfin_debug_mmrs_init()
914 D32(EBIU_DDRBRC7); in bfin_debug_mmrs_init()
915 D32(EBIU_DDRBWC0); in bfin_debug_mmrs_init()
916 D32(EBIU_DDRBWC1); in bfin_debug_mmrs_init()
917 D32(EBIU_DDRBWC2); in bfin_debug_mmrs_init()
918 D32(EBIU_DDRBWC3); in bfin_debug_mmrs_init()
919 D32(EBIU_DDRBWC4); in bfin_debug_mmrs_init()
920 D32(EBIU_DDRBWC5); in bfin_debug_mmrs_init()
921 D32(EBIU_DDRBWC6); in bfin_debug_mmrs_init()
922 D32(EBIU_DDRBWC7); in bfin_debug_mmrs_init()
923 D32(EBIU_DDRCTL0); in bfin_debug_mmrs_init()
924 D32(EBIU_DDRCTL1); in bfin_debug_mmrs_init()
925 D32(EBIU_DDRCTL2); in bfin_debug_mmrs_init()
926 D32(EBIU_DDRCTL3); in bfin_debug_mmrs_init()
927 D32(EBIU_DDRGC0); in bfin_debug_mmrs_init()
928 D32(EBIU_DDRGC1); in bfin_debug_mmrs_init()
929 D32(EBIU_DDRGC2); in bfin_debug_mmrs_init()
930 D32(EBIU_DDRGC3); in bfin_debug_mmrs_init()
931 D32(EBIU_DDRMCCL); in bfin_debug_mmrs_init()
932 D32(EBIU_DDRMCEN); in bfin_debug_mmrs_init()
933 D32(EBIU_DDRQUE); in bfin_debug_mmrs_init()
934 D32(EBIU_DDRTACT); in bfin_debug_mmrs_init()
935 D32(EBIU_ERRADD); in bfin_debug_mmrs_init()
942 D32(EMAC_ADDRHI); in bfin_debug_mmrs_init()
943 D32(EMAC_ADDRLO); in bfin_debug_mmrs_init()
944 D32(EMAC_FLC); in bfin_debug_mmrs_init()
945 D32(EMAC_HASHHI); in bfin_debug_mmrs_init()
946 D32(EMAC_HASHLO); in bfin_debug_mmrs_init()
947 D32(EMAC_MMC_CTL); in bfin_debug_mmrs_init()
948 D32(EMAC_MMC_RIRQE); in bfin_debug_mmrs_init()
949 D32(EMAC_MMC_RIRQS); in bfin_debug_mmrs_init()
950 D32(EMAC_MMC_TIRQE); in bfin_debug_mmrs_init()
951 D32(EMAC_MMC_TIRQS); in bfin_debug_mmrs_init()
952 D32(EMAC_OPMODE); in bfin_debug_mmrs_init()
953 D32(EMAC_RXC_ALIGN); in bfin_debug_mmrs_init()
954 D32(EMAC_RXC_ALLFRM); in bfin_debug_mmrs_init()
955 D32(EMAC_RXC_ALLOCT); in bfin_debug_mmrs_init()
956 D32(EMAC_RXC_BROAD); in bfin_debug_mmrs_init()
957 D32(EMAC_RXC_DMAOVF); in bfin_debug_mmrs_init()
958 D32(EMAC_RXC_EQ64); in bfin_debug_mmrs_init()
959 D32(EMAC_RXC_FCS); in bfin_debug_mmrs_init()
960 D32(EMAC_RXC_GE1024); in bfin_debug_mmrs_init()
961 D32(EMAC_RXC_LNERRI); in bfin_debug_mmrs_init()
962 D32(EMAC_RXC_LNERRO); in bfin_debug_mmrs_init()
963 D32(EMAC_RXC_LONG); in bfin_debug_mmrs_init()
964 D32(EMAC_RXC_LT1024); in bfin_debug_mmrs_init()
965 D32(EMAC_RXC_LT128); in bfin_debug_mmrs_init()
966 D32(EMAC_RXC_LT256); in bfin_debug_mmrs_init()
967 D32(EMAC_RXC_LT512); in bfin_debug_mmrs_init()
968 D32(EMAC_RXC_MACCTL); in bfin_debug_mmrs_init()
969 D32(EMAC_RXC_MULTI); in bfin_debug_mmrs_init()
970 D32(EMAC_RXC_OCTET); in bfin_debug_mmrs_init()
971 D32(EMAC_RXC_OK); in bfin_debug_mmrs_init()
972 D32(EMAC_RXC_OPCODE); in bfin_debug_mmrs_init()
973 D32(EMAC_RXC_PAUSE); in bfin_debug_mmrs_init()
974 D32(EMAC_RXC_SHORT); in bfin_debug_mmrs_init()
975 D32(EMAC_RXC_TYPED); in bfin_debug_mmrs_init()
976 D32(EMAC_RXC_UNICST); in bfin_debug_mmrs_init()
977 D32(EMAC_RX_IRQE); in bfin_debug_mmrs_init()
978 D32(EMAC_RX_STAT); in bfin_debug_mmrs_init()
979 D32(EMAC_RX_STKY); in bfin_debug_mmrs_init()
980 D32(EMAC_STAADD); in bfin_debug_mmrs_init()
981 D32(EMAC_STADAT); in bfin_debug_mmrs_init()
982 D32(EMAC_SYSCTL); in bfin_debug_mmrs_init()
983 D32(EMAC_SYSTAT); in bfin_debug_mmrs_init()
984 D32(EMAC_TXC_1COL); in bfin_debug_mmrs_init()
985 D32(EMAC_TXC_ABORT); in bfin_debug_mmrs_init()
986 D32(EMAC_TXC_ALLFRM); in bfin_debug_mmrs_init()
987 D32(EMAC_TXC_ALLOCT); in bfin_debug_mmrs_init()
988 D32(EMAC_TXC_BROAD); in bfin_debug_mmrs_init()
989 D32(EMAC_TXC_CRSERR); in bfin_debug_mmrs_init()
990 D32(EMAC_TXC_DEFER); in bfin_debug_mmrs_init()
991 D32(EMAC_TXC_DMAUND); in bfin_debug_mmrs_init()
992 D32(EMAC_TXC_EQ64); in bfin_debug_mmrs_init()
993 D32(EMAC_TXC_GE1024); in bfin_debug_mmrs_init()
994 D32(EMAC_TXC_GT1COL); in bfin_debug_mmrs_init()
995 D32(EMAC_TXC_LATECL); in bfin_debug_mmrs_init()
996 D32(EMAC_TXC_LT1024); in bfin_debug_mmrs_init()
997 D32(EMAC_TXC_LT128); in bfin_debug_mmrs_init()
998 D32(EMAC_TXC_LT256); in bfin_debug_mmrs_init()
999 D32(EMAC_TXC_LT512); in bfin_debug_mmrs_init()
1000 D32(EMAC_TXC_MACCTL); in bfin_debug_mmrs_init()
1001 D32(EMAC_TXC_MULTI); in bfin_debug_mmrs_init()
1002 D32(EMAC_TXC_OCTET); in bfin_debug_mmrs_init()
1003 D32(EMAC_TXC_OK); in bfin_debug_mmrs_init()
1004 D32(EMAC_TXC_UNICST); in bfin_debug_mmrs_init()
1005 D32(EMAC_TXC_XS_COL); in bfin_debug_mmrs_init()
1006 D32(EMAC_TXC_XS_DFR); in bfin_debug_mmrs_init()
1007 D32(EMAC_TX_IRQE); in bfin_debug_mmrs_init()
1008 D32(EMAC_TX_STAT); in bfin_debug_mmrs_init()
1009 D32(EMAC_TX_STKY); in bfin_debug_mmrs_init()
1010 D32(EMAC_VLAN1); in bfin_debug_mmrs_init()
1011 D32(EMAC_VLAN2); in bfin_debug_mmrs_init()
1012 D32(EMAC_WKUP_CTL); in bfin_debug_mmrs_init()
1013 D32(EMAC_WKUP_FFCMD); in bfin_debug_mmrs_init()
1014 D32(EMAC_WKUP_FFCRC0); in bfin_debug_mmrs_init()
1015 D32(EMAC_WKUP_FFCRC1); in bfin_debug_mmrs_init()
1016 D32(EMAC_WKUP_FFMSK0); in bfin_debug_mmrs_init()
1017 D32(EMAC_WKUP_FFMSK1); in bfin_debug_mmrs_init()
1018 D32(EMAC_WKUP_FFMSK2); in bfin_debug_mmrs_init()
1019 D32(EMAC_WKUP_FFMSK3); in bfin_debug_mmrs_init()
1020 D32(EMAC_WKUP_FFOFF); in bfin_debug_mmrs_init()
1022 D32(EMAC_PTP_ACCR); in bfin_debug_mmrs_init()
1023 D32(EMAC_PTP_ADDEND); in bfin_debug_mmrs_init()
1024 D32(EMAC_PTP_ALARMHI); in bfin_debug_mmrs_init()
1025 D32(EMAC_PTP_ALARMLO); in bfin_debug_mmrs_init()
1027 D32(EMAC_PTP_FOFF); in bfin_debug_mmrs_init()
1028 D32(EMAC_PTP_FV1); in bfin_debug_mmrs_init()
1029 D32(EMAC_PTP_FV2); in bfin_debug_mmrs_init()
1030 D32(EMAC_PTP_FV3); in bfin_debug_mmrs_init()
1032 D32(EMAC_PTP_ID_SNAP); in bfin_debug_mmrs_init()
1035 D32(EMAC_PTP_OFFSET); in bfin_debug_mmrs_init()
1036 D32(EMAC_PTP_PPS_PERIOD); in bfin_debug_mmrs_init()
1037 D32(EMAC_PTP_PPS_STARTHI); in bfin_debug_mmrs_init()
1038 D32(EMAC_PTP_PPS_STARTLO); in bfin_debug_mmrs_init()
1039 D32(EMAC_PTP_RXSNAPHI); in bfin_debug_mmrs_init()
1040 D32(EMAC_PTP_RXSNAPLO); in bfin_debug_mmrs_init()
1041 D32(EMAC_PTP_TIMEHI); in bfin_debug_mmrs_init()
1042 D32(EMAC_PTP_TIMELO); in bfin_debug_mmrs_init()
1043 D32(EMAC_PTP_TXSNAPHI); in bfin_debug_mmrs_init()
1044 D32(EMAC_PTP_TXSNAPLO); in bfin_debug_mmrs_init()
1136 D32(MXVR_PLL_CTL_0); in bfin_debug_mmrs_init()
1138 D32(MXVR_STATE_0); in bfin_debug_mmrs_init()
1139 D32(MXVR_STATE_1); in bfin_debug_mmrs_init()
1140 D32(MXVR_INT_STAT_0); in bfin_debug_mmrs_init()
1141 D32(MXVR_INT_STAT_1); in bfin_debug_mmrs_init()
1142 D32(MXVR_INT_EN_0); in bfin_debug_mmrs_init()
1143 D32(MXVR_INT_EN_1); in bfin_debug_mmrs_init()
1148 D32(MXVR_LADDR); in bfin_debug_mmrs_init()
1150 D32(MXVR_AADDR); in bfin_debug_mmrs_init()
1151 D32(MXVR_ALLOC_0); in bfin_debug_mmrs_init()
1152 D32(MXVR_ALLOC_1); in bfin_debug_mmrs_init()
1153 D32(MXVR_ALLOC_2); in bfin_debug_mmrs_init()
1154 D32(MXVR_ALLOC_3); in bfin_debug_mmrs_init()
1155 D32(MXVR_ALLOC_4); in bfin_debug_mmrs_init()
1156 D32(MXVR_ALLOC_5); in bfin_debug_mmrs_init()
1157 D32(MXVR_ALLOC_6); in bfin_debug_mmrs_init()
1158 D32(MXVR_ALLOC_7); in bfin_debug_mmrs_init()
1159 D32(MXVR_ALLOC_8); in bfin_debug_mmrs_init()
1160 D32(MXVR_ALLOC_9); in bfin_debug_mmrs_init()
1161 D32(MXVR_ALLOC_10); in bfin_debug_mmrs_init()
1162 D32(MXVR_ALLOC_11); in bfin_debug_mmrs_init()
1163 D32(MXVR_ALLOC_12); in bfin_debug_mmrs_init()
1164 D32(MXVR_ALLOC_13); in bfin_debug_mmrs_init()
1165 D32(MXVR_ALLOC_14); in bfin_debug_mmrs_init()
1166 D32(MXVR_SYNC_LCHAN_0); in bfin_debug_mmrs_init()
1167 D32(MXVR_SYNC_LCHAN_1); in bfin_debug_mmrs_init()
1168 D32(MXVR_SYNC_LCHAN_2); in bfin_debug_mmrs_init()
1169 D32(MXVR_SYNC_LCHAN_3); in bfin_debug_mmrs_init()
1170 D32(MXVR_SYNC_LCHAN_4); in bfin_debug_mmrs_init()
1171 D32(MXVR_SYNC_LCHAN_5); in bfin_debug_mmrs_init()
1172 D32(MXVR_SYNC_LCHAN_6); in bfin_debug_mmrs_init()
1173 D32(MXVR_SYNC_LCHAN_7); in bfin_debug_mmrs_init()
1174 D32(MXVR_DMA0_CONFIG); in bfin_debug_mmrs_init()
1175 D32(MXVR_DMA0_START_ADDR); in bfin_debug_mmrs_init()
1177 D32(MXVR_DMA0_CURR_ADDR); in bfin_debug_mmrs_init()
1179 D32(MXVR_DMA1_CONFIG); in bfin_debug_mmrs_init()
1180 D32(MXVR_DMA1_START_ADDR); in bfin_debug_mmrs_init()
1182 D32(MXVR_DMA1_CURR_ADDR); in bfin_debug_mmrs_init()
1184 D32(MXVR_DMA2_CONFIG); in bfin_debug_mmrs_init()
1185 D32(MXVR_DMA2_START_ADDR); in bfin_debug_mmrs_init()
1187 D32(MXVR_DMA2_CURR_ADDR); in bfin_debug_mmrs_init()
1189 D32(MXVR_DMA3_CONFIG); in bfin_debug_mmrs_init()
1190 D32(MXVR_DMA3_START_ADDR); in bfin_debug_mmrs_init()
1192 D32(MXVR_DMA3_CURR_ADDR); in bfin_debug_mmrs_init()
1194 D32(MXVR_DMA4_CONFIG); in bfin_debug_mmrs_init()
1195 D32(MXVR_DMA4_START_ADDR); in bfin_debug_mmrs_init()
1197 D32(MXVR_DMA4_CURR_ADDR); in bfin_debug_mmrs_init()
1199 D32(MXVR_DMA5_CONFIG); in bfin_debug_mmrs_init()
1200 D32(MXVR_DMA5_START_ADDR); in bfin_debug_mmrs_init()
1202 D32(MXVR_DMA5_CURR_ADDR); in bfin_debug_mmrs_init()
1204 D32(MXVR_DMA6_CONFIG); in bfin_debug_mmrs_init()
1205 D32(MXVR_DMA6_START_ADDR); in bfin_debug_mmrs_init()
1207 D32(MXVR_DMA6_CURR_ADDR); in bfin_debug_mmrs_init()
1209 D32(MXVR_DMA7_CONFIG); in bfin_debug_mmrs_init()
1210 D32(MXVR_DMA7_START_ADDR); in bfin_debug_mmrs_init()
1212 D32(MXVR_DMA7_CURR_ADDR); in bfin_debug_mmrs_init()
1215 D32(MXVR_APRB_START_ADDR); in bfin_debug_mmrs_init()
1216 D32(MXVR_APRB_CURR_ADDR); in bfin_debug_mmrs_init()
1217 D32(MXVR_APTB_START_ADDR); in bfin_debug_mmrs_init()
1218 D32(MXVR_APTB_CURR_ADDR); in bfin_debug_mmrs_init()
1219 D32(MXVR_CM_CTL); in bfin_debug_mmrs_init()
1220 D32(MXVR_CMRB_START_ADDR); in bfin_debug_mmrs_init()
1221 D32(MXVR_CMRB_CURR_ADDR); in bfin_debug_mmrs_init()
1222 D32(MXVR_CMTB_START_ADDR); in bfin_debug_mmrs_init()
1223 D32(MXVR_CMTB_CURR_ADDR); in bfin_debug_mmrs_init()
1224 D32(MXVR_RRDB_START_ADDR); in bfin_debug_mmrs_init()
1225 D32(MXVR_RRDB_CURR_ADDR); in bfin_debug_mmrs_init()
1226 D32(MXVR_PAT_DATA_0); in bfin_debug_mmrs_init()
1227 D32(MXVR_PAT_EN_0); in bfin_debug_mmrs_init()
1228 D32(MXVR_PAT_DATA_1); in bfin_debug_mmrs_init()
1229 D32(MXVR_PAT_EN_1); in bfin_debug_mmrs_init()
1232 D32(MXVR_ROUTING_0); in bfin_debug_mmrs_init()
1233 D32(MXVR_ROUTING_1); in bfin_debug_mmrs_init()
1234 D32(MXVR_ROUTING_2); in bfin_debug_mmrs_init()
1235 D32(MXVR_ROUTING_3); in bfin_debug_mmrs_init()
1236 D32(MXVR_ROUTING_4); in bfin_debug_mmrs_init()
1237 D32(MXVR_ROUTING_5); in bfin_debug_mmrs_init()
1238 D32(MXVR_ROUTING_6); in bfin_debug_mmrs_init()
1239 D32(MXVR_ROUTING_7); in bfin_debug_mmrs_init()
1240 D32(MXVR_ROUTING_8); in bfin_debug_mmrs_init()
1241 D32(MXVR_ROUTING_9); in bfin_debug_mmrs_init()
1242 D32(MXVR_ROUTING_10); in bfin_debug_mmrs_init()
1243 D32(MXVR_ROUTING_11); in bfin_debug_mmrs_init()
1244 D32(MXVR_ROUTING_12); in bfin_debug_mmrs_init()
1245 D32(MXVR_ROUTING_13); in bfin_debug_mmrs_init()
1246 D32(MXVR_ROUTING_14); in bfin_debug_mmrs_init()
1248 D32(MXVR_PLL_CTL_1); in bfin_debug_mmrs_init()
1252 D32(MXVR_CLK_CTL); in bfin_debug_mmrs_init()
1255 D32(MXVR_CDRPLL_CTL); in bfin_debug_mmrs_init()
1258 D32(MXVR_FMPLL_CTL); in bfin_debug_mmrs_init()
1293 D32(OTP_TIMING); in bfin_debug_mmrs_init()
1294 D32(OTP_DATA0); in bfin_debug_mmrs_init()
1295 D32(OTP_DATA1); in bfin_debug_mmrs_init()
1296 D32(OTP_DATA2); in bfin_debug_mmrs_init()
1297 D32(OTP_DATA3); in bfin_debug_mmrs_init()
1324 D32(PIXC_RYCON); in bfin_debug_mmrs_init()
1325 D32(PIXC_GUCON); in bfin_debug_mmrs_init()
1326 D32(PIXC_BVCON); in bfin_debug_mmrs_init()
1327 D32(PIXC_CCBIAS); in bfin_debug_mmrs_init()
1328 D32(PIXC_TC); in bfin_debug_mmrs_init()
1337 D32(CHIPID); /* it's part of this hardware block */ in bfin_debug_mmrs_init()
1373 D32(RSI_ARGUMENT); in bfin_debug_mmrs_init()
1381 D32(RSI_DATA_TIMER); in bfin_debug_mmrs_init()
1384 D32(RSI_FIFO); in bfin_debug_mmrs_init()
1386 D32(RSI_MASK0); in bfin_debug_mmrs_init()
1387 D32(RSI_MASK1); in bfin_debug_mmrs_init()
1398 D32(RSI_RESPONSE0); in bfin_debug_mmrs_init()
1399 D32(RSI_RESPONSE1); in bfin_debug_mmrs_init()
1400 D32(RSI_RESPONSE2); in bfin_debug_mmrs_init()
1401 D32(RSI_RESPONSE3); in bfin_debug_mmrs_init()
1403 D32(RSI_STATUS); in bfin_debug_mmrs_init()
1409 D32(RTC_ALARM); in bfin_debug_mmrs_init()
1413 D32(RTC_STAT); in bfin_debug_mmrs_init()
1419 D32(SDH_ARGUMENT); in bfin_debug_mmrs_init()
1426 D32(SDH_DATA_TIMER); in bfin_debug_mmrs_init()
1429 D32(SDH_FIFO); in bfin_debug_mmrs_init()
1431 D32(SDH_MASK0); in bfin_debug_mmrs_init()
1432 D32(SDH_MASK1); in bfin_debug_mmrs_init()
1456 D32(SECURE_SYSSWT); in bfin_debug_mmrs_init()
1463 D32(SIC_IAR0); in bfin_debug_mmrs_init()
1464 D32(SIC_IAR1); in bfin_debug_mmrs_init()
1465 D32(SIC_IAR2); in bfin_debug_mmrs_init()
1467 D32(SIC_IAR3); in bfin_debug_mmrs_init()
1470 D32(SIC_IAR4); in bfin_debug_mmrs_init()
1471 D32(SIC_IAR5); in bfin_debug_mmrs_init()
1472 D32(SIC_IAR6); in bfin_debug_mmrs_init()
1475 D32(SIC_IAR7); in bfin_debug_mmrs_init()
1478 D32(SIC_IAR8); in bfin_debug_mmrs_init()
1479 D32(SIC_IAR9); in bfin_debug_mmrs_init()
1480 D32(SIC_IAR10); in bfin_debug_mmrs_init()
1481 D32(SIC_IAR11); in bfin_debug_mmrs_init()
1484 D32(SIC_IMASK); in bfin_debug_mmrs_init()
1485 D32(SIC_ISR); in bfin_debug_mmrs_init()
1486 D32(SIC_IWR); in bfin_debug_mmrs_init()
1489 D32(SIC_IMASK0); in bfin_debug_mmrs_init()
1490 D32(SIC_IMASK1); in bfin_debug_mmrs_init()
1491 D32(SIC_ISR0); in bfin_debug_mmrs_init()
1492 D32(SIC_ISR1); in bfin_debug_mmrs_init()
1493 D32(SIC_IWR0); in bfin_debug_mmrs_init()
1494 D32(SIC_IWR1); in bfin_debug_mmrs_init()
1497 D32(SIC_IMASK2); in bfin_debug_mmrs_init()
1498 D32(SIC_ISR2); in bfin_debug_mmrs_init()
1499 D32(SIC_IWR2); in bfin_debug_mmrs_init()
1505 D32(SICB_IAR0); in bfin_debug_mmrs_init()
1506 D32(SICB_IAR1); in bfin_debug_mmrs_init()
1507 D32(SICB_IAR2); in bfin_debug_mmrs_init()
1508 D32(SICB_IAR3); in bfin_debug_mmrs_init()
1509 D32(SICB_IAR4); in bfin_debug_mmrs_init()
1510 D32(SICB_IAR5); in bfin_debug_mmrs_init()
1511 D32(SICB_IAR6); in bfin_debug_mmrs_init()
1512 D32(SICB_IAR7); in bfin_debug_mmrs_init()
1513 D32(SICB_IMASK0); in bfin_debug_mmrs_init()
1514 D32(SICB_IMASK1); in bfin_debug_mmrs_init()
1515 D32(SICB_ISR0); in bfin_debug_mmrs_init()
1516 D32(SICB_ISR1); in bfin_debug_mmrs_init()
1517 D32(SICB_IWR0); in bfin_debug_mmrs_init()
1518 D32(SICB_IWR1); in bfin_debug_mmrs_init()
1751 D32(WDOG_CNT); in bfin_debug_mmrs_init()
1753 D32(WDOG_STAT); in bfin_debug_mmrs_init()
1757 D32(WDOGA_CNT); in bfin_debug_mmrs_init()
1759 D32(WDOGA_STAT); in bfin_debug_mmrs_init()
1760 D32(WDOGB_CNT); in bfin_debug_mmrs_init()
1762 D32(WDOGB_STAT); in bfin_debug_mmrs_init()