Lines Matching refs:L
20 P0.L = lo(PLL_CTL);
23 W[P0] = R1.L;
39 P0.L = lo(PLL_CTL);
43 w[p0] = R7.L;
69 P3.L = lo(VR_CTL);
79 W[P3] = R4.L;
107 P0.L = lo(PLL_DIV);
109 R0.L = 0xF;
113 P0.L = lo(PLL_CTL);
115 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
124 P0.L = lo(VR_CTL);
145 P0.L = lo(PLL_CTL);
148 W[P0] = R0.L; /* Turn CCLK OFF */
161 P0.L = lo(VR_CTL);
172 P0.L = lo(PLL_DIV);
176 P0.L = lo(PLL_CTL);
195 P0.L = lo(EBIU_RSTCTL);
205 P0.L = lo(EBIU_SDGCTL);
207 P1.L = lo(EBIU_SDSTAT);
233 P0.L = lo(EBIU_RSTCTL);
239 P0.L = lo(EBIU_SDGCTL);
260 P0.L = lo(SYSMMR_BASE);
268 P0.L = lo(SIC_IWR);
278 P0.L = lo(PLL_STAT);
295 P1.L = _hibernate_mode;
300 R1.L = 0xBEEF;
302 R2.L = .Lpm_resume_here;