Lines Matching defs:quicc
53 typedef struct quicc { struct
55 struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */ argument
57 }ch_or_u; /* multipul or user space */
60 union {
89 } pram[4];
95 volatile unsigned long sim_mcr; /* module configuration reg */
96 volatile unsigned short sim_simtr; /* module test register */
97 volatile unsigned char RESERVED2[0x2]; /* Reserved area */
98 volatile unsigned char sim_avr; /* auto vector reg */
99 volatile unsigned char sim_rsr; /* reset status reg */
100 volatile unsigned char RESERVED3[0x2]; /* Reserved area */
101 volatile unsigned char sim_clkocr; /* CLCO control register */
102 volatile unsigned char RESERVED62[0x3]; /* Reserved area */
103 volatile unsigned short sim_pllcr; /* PLL control register */
104 volatile unsigned char RESERVED63[0x2]; /* Reserved area */
105 volatile unsigned short sim_cdvcr; /* Clock devider control register */
106 volatile unsigned short sim_pepar; /* Port E pin assignment register */
107 volatile unsigned char RESERVED64[0xa]; /* Reserved area */
108 volatile unsigned char sim_sypcr; /* system protection control*/
109 volatile unsigned char sim_swiv; /* software interrupt vector*/
110 volatile unsigned char RESERVED6[0x2]; /* Reserved area */
111 volatile unsigned short sim_picr; /* periodic interrupt control reg */
112 volatile unsigned char RESERVED7[0x2]; /* Reserved area */
113 volatile unsigned short sim_pitr; /* periodic interrupt timing reg */
114 volatile unsigned char RESERVED8[0x3]; /* Reserved area */
115 volatile unsigned char sim_swsr; /* software service */
116 volatile unsigned long sim_bkar; /* breakpoint address register*/
117 volatile unsigned long sim_bkcr; /* breakpoint control register*/
118 volatile unsigned char RESERVED10[0x8]; /* Reserved area */
120 volatile unsigned long memc_gmr; /* Global memory register */
121 volatile unsigned short memc_mstat; /* MEMC status register */
122 volatile unsigned char RESERVED11[0xa]; /* Reserved area */
123 volatile unsigned long memc_br0; /* base register 0 */
124 volatile unsigned long memc_or0; /* option register 0 */
125 volatile unsigned char RESERVED12[0x8]; /* Reserved area */
126 volatile unsigned long memc_br1; /* base register 1 */
127 volatile unsigned long memc_or1; /* option register 1 */
128 volatile unsigned char RESERVED13[0x8]; /* Reserved area */
129 volatile unsigned long memc_br2; /* base register 2 */
130 volatile unsigned long memc_or2; /* option register 2 */
131 volatile unsigned char RESERVED14[0x8]; /* Reserved area */
132 volatile unsigned long memc_br3; /* base register 3 */
133 volatile unsigned long memc_or3; /* option register 3 */
134 volatile unsigned char RESERVED15[0x8]; /* Reserved area */
135 volatile unsigned long memc_br4; /* base register 3 */
136 volatile unsigned long memc_or4; /* option register 3 */
137 volatile unsigned char RESERVED16[0x8]; /* Reserved area */
138 volatile unsigned long memc_br5; /* base register 3 */
139 volatile unsigned long memc_or5; /* option register 3 */
140 volatile unsigned char RESERVED17[0x8]; /* Reserved area */
141 volatile unsigned long memc_br6; /* base register 3 */
142 volatile unsigned long memc_or6; /* option register 3 */
143 volatile unsigned char RESERVED18[0x8]; /* Reserved area */
144 volatile unsigned long memc_br7; /* base register 3 */
145 volatile unsigned long memc_or7; /* option register 3 */
146 volatile unsigned char RESERVED9[0x28]; /* Reserved area */
148 volatile unsigned short test_tstmra; /* master shift a */
149 volatile unsigned short test_tstmrb; /* master shift b */
150 volatile unsigned short test_tstsc; /* shift count */
151 volatile unsigned short test_tstrc; /* repetition counter */
152 volatile unsigned short test_creg; /* control */
153 volatile unsigned short test_dreg; /* destributed register */
154 volatile unsigned char RESERVED58[0x404]; /* Reserved area */
156 volatile unsigned short idma_iccr; /* channel configuration reg*/
157 volatile unsigned char RESERVED19[0x2]; /* Reserved area */
158 volatile unsigned short idma1_cmr; /* dma mode reg */
159 volatile unsigned char RESERVED68[0x2]; /* Reserved area */
160 volatile unsigned long idma1_sapr; /* dma source addr ptr */
161 volatile unsigned long idma1_dapr; /* dma destination addr ptr */
162 volatile unsigned long idma1_bcr; /* dma byte count reg */
163 volatile unsigned char idma1_fcr; /* function code reg */
164 volatile unsigned char RESERVED20; /* Reserved area */
165 volatile unsigned char idma1_cmar; /* channel mask reg */
166 volatile unsigned char RESERVED21; /* Reserved area */
167 volatile unsigned char idma1_csr; /* channel status reg */
168 volatile unsigned char RESERVED22[0x3]; /* Reserved area */
170 volatile unsigned char sdma_sdsr; /* status reg */
171 volatile unsigned char RESERVED23; /* Reserved area */
172 volatile unsigned short sdma_sdcr; /* configuration reg */
173 volatile unsigned long sdma_sdar; /* address reg */
175 volatile unsigned char RESERVED69[0x2]; /* Reserved area */
176 volatile unsigned short idma2_cmr; /* dma mode reg */
177 volatile unsigned long idma2_sapr; /* dma source addr ptr */
178 volatile unsigned long idma2_dapr; /* dma destination addr ptr */
179 volatile unsigned long idma2_bcr; /* dma byte count reg */
180 volatile unsigned char idma2_fcr; /* function code reg */
181 volatile unsigned char RESERVED24; /* Reserved area */
182 volatile unsigned char idma2_cmar; /* channel mask reg */
183 volatile unsigned char RESERVED25; /* Reserved area */
184 volatile unsigned char idma2_csr; /* channel status reg */
185 volatile unsigned char RESERVED26[0x7]; /* Reserved area */
187 volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
188 volatile unsigned long intr_cipr; /* CP interrupt pending reg */
189 volatile unsigned long intr_cimr; /* CP interrupt mask reg */
190 volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
192 volatile unsigned short pio_padir; /* port A data direction reg */
193 volatile unsigned short pio_papar; /* port A pin assignment reg */
194 volatile unsigned short pio_paodr; /* port A open drain reg */
195 volatile unsigned short pio_padat; /* port A data register */
196 volatile unsigned char RESERVED28[0x8]; /* Reserved area */
197 volatile unsigned short pio_pcdir; /* port C data direction reg*/
198 volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
199 volatile unsigned short pio_pcso; /* port C special options */
200 volatile unsigned short pio_pcdat; /* port C data register */
201 volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
202 volatile unsigned char RESERVED29[0x16]; /* Reserved area */
204 volatile unsigned short timer_tgcr; /* timer global configuration reg */
205 volatile unsigned char RESERVED30[0xe]; /* Reserved area */
206 volatile unsigned short timer_tmr1; /* timer 1 mode reg */
207 volatile unsigned short timer_tmr2; /* timer 2 mode reg */
208 volatile unsigned short timer_trr1; /* timer 1 referance reg */
209 volatile unsigned short timer_trr2; /* timer 2 referance reg */
210 volatile unsigned short timer_tcr1; /* timer 1 capture reg */
211 volatile unsigned short timer_tcr2; /* timer 2 capture reg */
212 volatile unsigned short timer_tcn1; /* timer 1 counter reg */
213 volatile unsigned short timer_tcn2; /* timer 2 counter reg */
214 volatile unsigned short timer_tmr3; /* timer 3 mode reg */
215 volatile unsigned short timer_tmr4; /* timer 4 mode reg */
216 volatile unsigned short timer_trr3; /* timer 3 referance reg */
217 volatile unsigned short timer_trr4; /* timer 4 referance reg */
218 volatile unsigned short timer_tcr3; /* timer 3 capture reg */
219 volatile unsigned short timer_tcr4; /* timer 4 capture reg */
220 volatile unsigned short timer_tcn3; /* timer 3 counter reg */
221 volatile unsigned short timer_tcn4; /* timer 4 counter reg */
222 volatile unsigned short timer_ter1; /* timer 1 event reg */
223 volatile unsigned short timer_ter2; /* timer 2 event reg */
224 volatile unsigned short timer_ter3; /* timer 3 event reg */
225 volatile unsigned short timer_ter4; /* timer 4 event reg */
226 volatile unsigned char RESERVED34[0x8]; /* Reserved area */
228 volatile unsigned short cp_cr; /* command register */
229 volatile unsigned char RESERVED35[0x2]; /* Reserved area */
230 volatile unsigned short cp_rccr; /* main configuration reg */
231 volatile unsigned char RESERVED37; /* Reserved area */
232 volatile unsigned char cp_rmds; /* development support status reg */
233 volatile unsigned long cp_rmdr; /* development support control reg */
234 volatile unsigned short cp_rctr1; /* ram break register 1 */
235 volatile unsigned short cp_rctr2; /* ram break register 2 */
236 volatile unsigned short cp_rctr3; /* ram break register 3 */
237 volatile unsigned short cp_rctr4; /* ram break register 4 */
238 volatile unsigned char RESERVED59[0x2]; /* Reserved area */
239 volatile unsigned short cp_rter; /* RISC timers event reg */
240 volatile unsigned char RESERVED38[0x2]; /* Reserved area */
241 volatile unsigned short cp_rtmr; /* RISC timers mask reg */
242 volatile unsigned char RESERVED39[0x14]; /* Reserved area */
244 union {
255 } brgc[4]; /* BRG1-BRG4 configuration regs*/
257 struct scc_regs {
312 } scc_regs[4];
314 struct smc_regs {
322 } smc_regs[2];
324 volatile unsigned short spi_spmode; /* SPI mode reg */
325 volatile unsigned char RESERVED51[0x4]; /* Reserved area */
326 volatile unsigned char spi_spie; /* SPI event reg */
327 volatile unsigned char RESERVED52[0x3]; /* Reserved area */
328 volatile unsigned char spi_spim; /* SPI mask reg */
329 volatile unsigned char RESERVED53[0x2]; /* Reserved area */
330 volatile unsigned char spi_spcom; /* SPI command reg */
331 volatile unsigned char RESERVED54[0x4]; /* Reserved area */
333 volatile unsigned short pip_pipc; /* pip configuration reg */
334 volatile unsigned char RESERVED65[0x2]; /* Reserved area */
335 volatile unsigned short pip_ptpr; /* pip timing parameters reg */
336 volatile unsigned long pip_pbdir; /* port b data direction reg */
337 volatile unsigned long pip_pbpar; /* port b pin assignment reg */
338 volatile unsigned long pip_pbodr; /* port b open drain reg */
339 volatile unsigned long pip_pbdat; /* port b data reg */
340 volatile unsigned char RESERVED71[0x18]; /* Reserved area */
342 volatile unsigned long si_simode; /* SI mode register */
343 volatile unsigned char si_sigmr; /* SI global mode register */
344 volatile unsigned char RESERVED55; /* Reserved area */
345 volatile unsigned char si_sistr; /* SI status register */
346 volatile unsigned char si_sicmr; /* SI command register */
347 volatile unsigned char RESERVED56[0x4]; /* Reserved area */
348 volatile unsigned long si_sicr; /* SI clock routing */
349 volatile unsigned long si_sirp; /* SI ram pointers */
350 volatile unsigned char RESERVED57[0xc]; /* Reserved area */
351 volatile unsigned short si_siram[0x80]; /* SI routing ram */