57 	__raw_writel(TCR_BASE, &tmrptr->tcr);  in txx9_clocksource_init()
58 	__raw_writel(0, &tmrptr->tisr);  in txx9_clocksource_init()
59 	__raw_writel(TIMER_CCD, &tmrptr->ccdr);  in txx9_clocksource_init()
60 	__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);  in txx9_clocksource_init()
61 	__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);  in txx9_clocksource_init()
62 	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9_clocksource_init()
74 	__raw_writel(TCR_BASE, &tmrptr->tcr);  in txx9tmr_stop_and_clear()
76 	__raw_writel(0, &tmrptr->tisr);  in txx9tmr_stop_and_clear()
89 		__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE,  in txx9tmr_set_mode()
92 		__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>  in txx9tmr_set_mode()
95 		__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9tmr_set_mode()
99 		__raw_writel(0, &tmrptr->itmr);  in txx9tmr_set_mode()
102 		__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);  in txx9tmr_set_mode()
105 		__raw_writel(TIMER_CCD, &tmrptr->ccdr);  in txx9tmr_set_mode()
106 		__raw_writel(0, &tmrptr->itmr);  in txx9tmr_set_mode()
120 	__raw_writel(delta, &tmrptr->cpra);  in txx9tmr_set_next_event()
121 	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9tmr_set_next_event()
142 	__raw_writel(0, &tmrptr->tisr); /* ack interrupt */  in txx9tmr_interrupt()
162 	__raw_writel(TIMER_CCD, &tmrptr->ccdr);  in txx9_clockevent_init()
163 	__raw_writel(0, &tmrptr->itmr);  in txx9_clockevent_init()
184 	__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9_tmr_init()
186 	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);  in txx9_tmr_init()
187 	__raw_writel(0, &tmrptr->tisr);  in txx9_tmr_init()
188 	__raw_writel(0xffffffff, &tmrptr->cpra);  in txx9_tmr_init()
189 	__raw_writel(0, &tmrptr->itmr);  in txx9_tmr_init()
190 	__raw_writel(0, &tmrptr->ccdr);  in txx9_tmr_init()
191 	__raw_writel(0, &tmrptr->pgmr);  in txx9_tmr_init()