Lines Matching refs:ir
854 mips_instruction ir) in cop1_cfc() argument
859 switch (MIPSInst_RD(ir)) { in cop1_cfc()
863 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
873 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
881 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
892 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
903 if (MIPSInst_RT(ir)) in cop1_cfc()
904 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
911 mips_instruction ir) in cop1_ctc() argument
917 if (MIPSInst_RT(ir) == 0) in cop1_ctc()
920 value = xcp->regs[MIPSInst_RT(ir)]; in cop1_ctc()
922 switch (MIPSInst_RD(ir)) { in cop1_ctc()
925 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
936 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
947 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
956 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
981 mips_instruction ir; in cop1Emulate() local
1021 ir = dec_insn.next_insn; /* process delay slot instr */ in cop1Emulate()
1024 ir = dec_insn.insn; /* process current instr */ in cop1Emulate()
1045 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) in cop1Emulate()
1053 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1055 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1056 MIPSInst_SIMM(ir)); in cop1Emulate()
1069 DITOREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1073 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1074 MIPSInst_SIMM(ir)); in cop1Emulate()
1076 DIFROMREG(dval, MIPSInst_RT(ir)); in cop1Emulate()
1090 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1091 MIPSInst_SIMM(ir)); in cop1Emulate()
1103 SITOREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1107 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1108 MIPSInst_SIMM(ir)); in cop1Emulate()
1110 SIFROMREG(wval, MIPSInst_RT(ir)); in cop1Emulate()
1124 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1130 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1131 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1132 MIPSInst_RD(ir)); in cop1Emulate()
1141 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1149 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1150 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1151 MIPSInst_RD(ir)); in cop1Emulate()
1160 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1165 if (MIPSInst_RT(ir) != 0) { in cop1Emulate()
1166 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1167 MIPSInst_RD(ir)); in cop1Emulate()
1173 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1178 cop1_cfc(xcp, ctx, ir); in cop1Emulate()
1183 cop1_ctc(xcp, ctx, ir); in cop1Emulate()
1195 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)]; in cop1Emulate()
1197 switch (MIPSInst_RS(ir)) { in cop1Emulate()
1212 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1218 switch (MIPSInst_RT(ir) & 3) { in cop1Emulate()
1249 contpc = MIPSInst_SIMM(ir); in cop1Emulate()
1250 ir = dec_insn.next_insn; in cop1Emulate()
1256 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { in cop1Emulate()
1266 ir = (ir & (~0xffff)) | MM_NOP16; in cop1Emulate()
1272 sig = mips_dsemul(xcp, ir, in cop1Emulate()
1287 switch (MIPSInst_OPCODE(ir)) { in cop1Emulate()
1310 switch (MIPSInst_FUNC(ir)) { in cop1Emulate()
1328 sig = mips_dsemul(xcp, ir, bcpc, contpc); in cop1Emulate()
1350 if (!(MIPSInst_RS(ir) & 0x10)) in cop1Emulate()
1354 if ((sig = fpu_emu(xcp, ctx, ir))) in cop1Emulate()
1363 sig = fpux_emu(xcp, ctx, ir, fault_addr); in cop1Emulate()
1372 if (MIPSInst_FUNC(ir) != movc_op) in cop1Emulate()
1374 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in cop1Emulate()
1375 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) in cop1Emulate()
1376 xcp->regs[MIPSInst_RD(ir)] = in cop1Emulate()
1377 xcp->regs[MIPSInst_RS(ir)]; in cop1Emulate()
1465 mips_instruction ir, void *__user *fault_addr) in fpux_emu() argument
1471 switch (MIPSInst_FMA_FFMT(ir)) { in fpux_emu()
1479 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1481 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1482 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1495 SITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1499 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1500 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1504 SIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1531 SPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1532 SPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1533 SPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1535 SPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1576 switch (MIPSInst_FUNC(ir)) { in fpux_emu()
1578 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1579 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1592 DITOREG(val, MIPSInst_FD(ir)); in fpux_emu()
1596 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1597 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1600 DIFROMREG(val, MIPSInst_FS(ir)); in fpux_emu()
1627 DPFROMREG(fr, MIPSInst_FR(ir)); in fpux_emu()
1628 DPFROMREG(fs, MIPSInst_FS(ir)); in fpux_emu()
1629 DPFROMREG(ft, MIPSInst_FT(ir)); in fpux_emu()
1631 DPTOREG(fd, MIPSInst_FD(ir)); in fpux_emu()
1641 if (MIPSInst_FUNC(ir) != pfetch_op) in fpux_emu()
1660 mips_instruction ir) in fpu_emu() argument
1676 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { in fpu_emu()
1684 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
1730 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
1732 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
1734 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1741 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1743 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1750 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1752 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1759 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
1763 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1770 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
1772 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1783 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1784 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1785 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
1796 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1797 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1798 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
1809 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1821 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1833 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1834 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1845 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1846 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1857 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1858 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1869 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1870 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1885 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1890 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1891 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
1896 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1927 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1933 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1946 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1947 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
1957 SPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
1959 SPFROMREG(rv.s, MIPSInst_FT(ir)); in fpu_emu()
1961 SPFROMREG(rv.s, MIPSInst_FS(ir)); in fpu_emu()
1968 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1981 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1982 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
1989 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
1990 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
1993 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
1994 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2018 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2061 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; in fpu_emu()
2063 ((MIPSInst_FT(ir) & 1) != 0)) in fpu_emu()
2065 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2071 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
2073 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2079 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
2081 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2088 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2092 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2099 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2101 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2112 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2113 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2114 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2125 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2126 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2127 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2138 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2150 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2162 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2163 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2174 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2175 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2186 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2187 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2198 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2199 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2214 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2219 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2220 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2225 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2233 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2242 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2255 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2256 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2266 DPFROMREG(fd, MIPSInst_FD(ir)); in fpu_emu()
2268 DPFROMREG(rv.d, MIPSInst_FT(ir)); in fpu_emu()
2270 DPFROMREG(rv.d, MIPSInst_FS(ir)); in fpu_emu()
2277 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2290 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2291 ieee754_csr.rm = MIPSInst_FUNC(ir); in fpu_emu()
2298 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) { in fpu_emu()
2299 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; in fpu_emu()
2302 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2303 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2327 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2330 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2336 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2346 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; in fpu_emu()
2347 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; in fpu_emu()
2352 (MIPSInst_FUNC(ir) & 0x20)) in fpu_emu()
2361 SPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2362 SPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2365 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2406 DIFROMREG(bits, MIPSInst_FS(ir)); in fpu_emu()
2408 switch (MIPSInst_FUNC(ir)) { in fpu_emu()
2421 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK; in fpu_emu()
2422 int sig = MIPSInst_FUNC(ir) & SIGN_BIT; in fpu_emu()
2426 (MIPSInst_FUNC(ir) & 0x20)) in fpu_emu()
2435 DPFROMREG(fs, MIPSInst_FS(ir)); in fpu_emu()
2436 DPFROMREG(ft, MIPSInst_FT(ir)); in fpu_emu()
2439 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) { in fpu_emu()
2497 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; in fpu_emu()
2507 DPTOREG(rv.d, MIPSInst_FD(ir)); in fpu_emu()
2510 SPTOREG(rv.s, MIPSInst_FD(ir)); in fpu_emu()
2513 SITOREG(rv.w, MIPSInst_FD(ir)); in fpu_emu()
2519 DITOREG(rv.l, MIPSInst_FD(ir)); in fpu_emu()