Lines Matching refs:s
59 } s; member
266 pci_addr.s.upper = 2; in octeon_read_config()
267 pci_addr.s.io = 1; in octeon_read_config()
268 pci_addr.s.did = 3; in octeon_read_config()
269 pci_addr.s.subdid = 1; in octeon_read_config()
270 pci_addr.s.endian_swap = 1; in octeon_read_config()
271 pci_addr.s.bus = bus->number; in octeon_read_config()
272 pci_addr.s.dev = devfn >> 3; in octeon_read_config()
273 pci_addr.s.func = devfn & 0x7; in octeon_read_config()
274 pci_addr.s.reg = reg; in octeon_read_config()
300 pci_addr.s.upper = 2; in octeon_write_config()
301 pci_addr.s.io = 1; in octeon_write_config()
302 pci_addr.s.did = 3; in octeon_write_config()
303 pci_addr.s.subdid = 1; in octeon_write_config()
304 pci_addr.s.endian_swap = 1; in octeon_write_config()
305 pci_addr.s.bus = bus->number; in octeon_write_config()
306 pci_addr.s.dev = devfn >> 3; in octeon_write_config()
307 pci_addr.s.func = devfn & 0x7; in octeon_write_config()
308 pci_addr.s.reg = reg; in octeon_write_config()
378 ctl_status.s.max_word = 1; in octeon_pci_initialize()
379 ctl_status.s.timer = 1; in octeon_pci_initialize()
390 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set in octeon_pci_initialize()
392 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ in octeon_pci_initialize()
393 ctl_status_2.s.bar2_enb = 1; in octeon_pci_initialize()
394 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ in octeon_pci_initialize()
395 ctl_status_2.s.bar2_esx = 1; in octeon_pci_initialize()
396 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ in octeon_pci_initialize()
399 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; in octeon_pci_initialize()
400 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ in octeon_pci_initialize()
401 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ in octeon_pci_initialize()
402 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ in octeon_pci_initialize()
403 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ in octeon_pci_initialize()
404 ctl_status_2.s.bb0 = 1; /* BAR0 is big */ in octeon_pci_initialize()
412 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", in octeon_pci_initialize()
413 ctl_status_2.s.ap_64ad ? "64" : "32"); in octeon_pci_initialize()
425 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / in octeon_pci_initialize()
438 if (ctl_status_2.s.ap_pcix) { in octeon_pci_initialize()
452 cfg19.s.tdomc = 4; in octeon_pci_initialize()
464 cfg19.s.mdrrmc = 2; in octeon_pci_initialize()
476 cfg19.s.mrbcm = 1; in octeon_pci_initialize()
482 cfg01.s.msae = 1; /* Memory Space Access Enable */ in octeon_pci_initialize()
483 cfg01.s.me = 1; /* Master Enable */ in octeon_pci_initialize()
484 cfg01.s.pee = 1; /* PERR# Enable */ in octeon_pci_initialize()
485 cfg01.s.see = 1; /* System Error Enable */ in octeon_pci_initialize()
486 cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ in octeon_pci_initialize()
500 pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ in octeon_pci_initialize()
511 cfg16.s.mltd = 1; /* Master Latency Timer Disable */ in octeon_pci_initialize()
520 cfg22.s.mrv = 0xff; in octeon_pci_initialize()
525 cfg22.s.flush = 1; in octeon_pci_initialize()
536 cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ in octeon_pci_initialize()
537 cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ in octeon_pci_initialize()
538 cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ in octeon_pci_initialize()
539 cfg56.s.roe = 1; /* Relaxed Ordering Enable */ in octeon_pci_initialize()
540 cfg56.s.mmbc = 1; /* Maximum Memory Byte Count in octeon_pci_initialize()
542 cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 in octeon_pci_initialize()
602 mem_access.s.esr = 1; /* Endian-Swap on read. */ in octeon_pci_setup()
603 mem_access.s.esw = 1; /* Endian-Swap on write. */ in octeon_pci_setup()
604 mem_access.s.nsr = 0; /* No-Snoop on read. */ in octeon_pci_setup()
605 mem_access.s.nsw = 0; /* No-Snoop on write. */ in octeon_pci_setup()
606 mem_access.s.ror = 0; /* Relax Read on read. */ in octeon_pci_setup()
607 mem_access.s.row = 0; /* Relax Order on write. */ in octeon_pci_setup()
608 mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ in octeon_pci_setup()
641 bar1_index.s.addr_idx = in octeon_pci_setup()
644 bar1_index.s.ca = 1; in octeon_pci_setup()
646 bar1_index.s.end_swp = 1; in octeon_pci_setup()
648 bar1_index.s.addr_v = 1; in octeon_pci_setup()
677 bar1_index.s.addr_idx = in octeon_pci_setup()
680 bar1_index.s.ca = 1; in octeon_pci_setup()
682 bar1_index.s.end_swp = 1; in octeon_pci_setup()
684 bar1_index.s.addr_v = 1; in octeon_pci_setup()