95 static u32 __init find_cap(int bus, int slot, int func, int cap)  in find_cap()  argument
100 	if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &  in find_cap()
104 	pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);  in find_cap()
109 		id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);  in find_cap()
114 		pos = read_pci_config_byte(bus, slot, func,  in find_cap()
121 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)  in read_agp()  argument
130 	pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);  in read_agp()
131 	apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);  in read_agp()
134 		       bus, slot, func);  in read_agp()
150 	aper_low = read_pci_config(bus, slot, func, 0x10);  in read_agp()
151 	aper_hi = read_pci_config(bus, slot, func, 0x14);  in read_agp()
159 		bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,  in read_agp()
163 			bus, slot, func, 32 << *order, apsizereg);  in read_agp()
168 		bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,  in read_agp()
191 	int bus, slot, func;  in search_agp_bridge()  local
195 		for (slot = 0; slot < 32; slot++) {  in search_agp_bridge()
199 				class = read_pci_config(bus, slot, func,  in search_agp_bridge()
208 					cap = find_cap(bus, slot, func,  in search_agp_bridge()
213 					return read_agp(bus, slot, func, cap,  in search_agp_bridge()
218 				type = read_pci_config_byte(bus, slot, func,  in search_agp_bridge()
259 	int i, fix, slot, valid_agp = 0;  in early_gart_iommu_check()  local
280 		for (slot = dev_base; slot < dev_limit; slot++) {  in early_gart_iommu_check()
281 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in early_gart_iommu_check()
284 			ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);  in early_gart_iommu_check()
288 			aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;  in early_gart_iommu_check()
336 		for (slot = dev_base; slot < dev_limit; slot++) {  in early_gart_iommu_check()
337 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in early_gart_iommu_check()
340 			ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);  in early_gart_iommu_check()
342 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in early_gart_iommu_check()
355 	int fix, slot, valid_agp = 0;  in gart_iommu_hole_init()  local
378 		for (slot = dev_base; slot < dev_limit; slot++) {  in gart_iommu_hole_init()
379 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in gart_iommu_hole_init()
386 			ctl = read_pci_config(bus, slot, 3,  in gart_iommu_hole_init()
396 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in gart_iommu_hole_init()
400 			aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;  in gart_iommu_hole_init()
490 		for (slot = dev_base; slot < dev_limit; slot++) {  in gart_iommu_hole_init()
491 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in gart_iommu_hole_init()
494 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in gart_iommu_hole_init()
495 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);  in gart_iommu_hole_init()