50 #define P(a, b) PERF_MEM_S(a, b)  macro
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
55 	P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
56 	OP_LH | P(LVL, L1)  | P(SNOOP, NONE),	/* 0x01: L1 local */
57 	OP_LH | P(LVL, LFB) | P(SNOOP, NONE),	/* 0x02: LFB hit */
58 	OP_LH | P(LVL, L2)  | P(SNOOP, NONE),	/* 0x03: L2 hit */
59 	OP_LH | P(LVL, L3)  | P(SNOOP, NONE),	/* 0x04: L3 hit */
60 	OP_LH | P(LVL, L3)  | P(SNOOP, MISS),	/* 0x05: L3 hit, snoop miss */
61 	OP_LH | P(LVL, L3)  | P(SNOOP, HIT),	/* 0x06: L3 hit, snoop hit */
62 	OP_LH | P(LVL, L3)  | P(SNOOP, HITM),	/* 0x07: L3 hit, snoop hitm */
63 	OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
64 	OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
65 	OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
66 	OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
67 	OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
68 	OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
69 	OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
70 	OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
76 	u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);  in precise_store_data()
88 		val |= P(TLB, MISS);  in precise_store_data()
90 		val |= P(TLB, HIT);  in precise_store_data()
98 		val |= P(LVL, HIT);  in precise_store_data()
100 		val |= P(LVL, MISS);  in precise_store_data()
106 		val |= P(LOCK, LOCKED);  in precise_store_data()
158 		val |= P(TLB, NA) | P(LOCK, NA);  in load_latency_data()
167 		val |= P(TLB, MISS) | P(TLB, L2);  in load_latency_data()
169 		val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);  in load_latency_data()
175 		val |= P(LOCK, LOCKED);  in load_latency_data()