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Lines Matching refs:writel

156 		writel(m, dmac + S6_DMA_TERMCNTIRQCLR);  in s6dmac_termcnt_irq()
165 writel(m, dmac + S6_DMA_PENDCNTIRQCLR); in s6dmac_pendcnt_irq()
173 writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR); in s6dmac_lowwmark_irq()
189 writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); in s6dmac_set_terminal_count()
216 writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) in s6dmac_disable_chan()
228 writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK); in s6dmac_set_stride_skip()
229 writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP); in s6dmac_set_stride_skip()
230 writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP); in s6dmac_set_stride_skip()
245 writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB); in s6dmac_enable_chan()
246 writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO); in s6dmac_enable_chan()
247 writel(lowwmark << S6_DMA_CHNCTRL_LOWWMARK, in s6dmac_enable_chan()
250 writel(((enable ? 1 : 0) << S6_DMA_CHNCTRL_ENABLE) | in s6dmac_enable_chan()
277 writel(mask, dmac + S6_DMA_TERMCNTIRQCLR); in _s6dmac_disable_error_irqs()
278 writel(mask, dmac + S6_DMA_PENDCNTIRQCLR); in _s6dmac_disable_error_irqs()
279 writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR); in _s6dmac_disable_error_irqs()
280 writel(readl(dmac + S6_DMA_INTENABLE0) in _s6dmac_disable_error_irqs()
283 writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL), in _s6dmac_disable_error_irqs()
285 writel((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER), in _s6dmac_disable_error_irqs()
287 writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1); in _s6dmac_disable_error_irqs()
339 writel(src, dmac + S6_DMA_DESCRFIFO0); in s6dmac_put_fifo()
340 writel(dst, dmac + S6_DMA_DESCRFIFO1); in s6dmac_put_fifo()
341 writel(size, dmac + S6_DMA_DESCRFIFO2); in s6dmac_put_fifo()
342 writel(chan, dmac + S6_DMA_DESCRFIFO3); in s6dmac_put_fifo()
364 writel((mask[nrch - 1] << S6_DMA_DPORTCTRLGRP_NRCHANS) in s6dmac_dp_setup_group()
378 writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port)); in s6dmac_dp_switch_group()