Lines Matching refs:lli
115 struct lli { struct
124 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)), argument
286 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */
339 struct lli *lli, dma_addr_t dma_lli,
572 struct lli *lli, dma_addr_t dma_lli, in map_sg_to_lli() argument
584 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli, in map_sg_to_lli()
637 lli[idx].dar = cpu_to_le32(addr); in map_sg_to_lli()
638 lli[idx].sar = cpu_to_le32((u32)dmadr_addr); in map_sg_to_lli()
640 lli[idx].ctl.low = cpu_to_le32( in map_sg_to_lli()
653 lli[idx].sar = cpu_to_le32(addr); in map_sg_to_lli()
654 lli[idx].dar = cpu_to_le32((u32)dmadr_addr); in map_sg_to_lli()
656 lli[idx].ctl.low = cpu_to_le32( in map_sg_to_lli()
675 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\ in map_sg_to_lli()
682 lli))); in map_sg_to_lli()
687 lli[idx].llp = cpu_to_le32(next_llp); in map_sg_to_lli()
701 lli[idx-1].llp = 0x00000000; in map_sg_to_lli()
702 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32; in map_sg_to_lli()
705 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx), in map_sg_to_lli()
727 struct lli *lli, dma_addr_t dma_lli, in dma_dwc_xfer_setup() argument
741 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir); in dma_dwc_xfer_setup()
745 lli, (u32)dma_lli, addr, num_lli); in dma_dwc_xfer_setup()