228 static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)  in __combo_phy_reg_read()  argument
231 	u8 dev = port_data[sata_port].phy_devs;  in __combo_phy_reg_read()
233 	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);  in __combo_phy_reg_read()
234 	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));  in __combo_phy_reg_read()
239 static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)  in __combo_phy_reg_write()  argument
241 	u8 dev = port_data[sata_port].phy_devs;  in __combo_phy_reg_write()
243 	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);  in __combo_phy_reg_write()
244 	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));  in __combo_phy_reg_write()
248 static void combo_phy_wait_for_ready(u8 sata_port)  in combo_phy_wait_for_ready()  argument
250 	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)  in combo_phy_wait_for_ready()
254 static u32 combo_phy_read(u8 sata_port, u32 addr)  in combo_phy_read()  argument
256 	combo_phy_wait_for_ready(sata_port);  in combo_phy_read()
257 	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);  in combo_phy_read()
258 	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);  in combo_phy_read()
259 	combo_phy_wait_for_ready(sata_port);  in combo_phy_read()
260 	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);  in combo_phy_read()
263 static void combo_phy_write(u8 sata_port, u32 addr, u32 data)  in combo_phy_write()  argument
265 	combo_phy_wait_for_ready(sata_port);  in combo_phy_write()
266 	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);  in combo_phy_write()
267 	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);  in combo_phy_write()
268 	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);  in combo_phy_write()
271 static void highbank_cphy_disable_overrides(u8 sata_port)  in highbank_cphy_disable_overrides()  argument
273 	u8 lane = port_data[sata_port].lane_mapping;  in highbank_cphy_disable_overrides()
275 	if (unlikely(port_data[sata_port].phy_base == NULL))  in highbank_cphy_disable_overrides()
277 	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);  in highbank_cphy_disable_overrides()
279 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in highbank_cphy_disable_overrides()
282 static void cphy_override_tx_attenuation(u8 sata_port, u32 val)  in cphy_override_tx_attenuation()  argument
284 	u8 lane = port_data[sata_port].lane_mapping;  in cphy_override_tx_attenuation()
290 	tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);  in cphy_override_tx_attenuation()
292 	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_tx_attenuation()
295 	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_tx_attenuation()
298 	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_tx_attenuation()
301 static void cphy_override_rx_mode(u8 sata_port, u32 val)  in cphy_override_rx_mode()  argument
303 	u8 lane = port_data[sata_port].lane_mapping;  in cphy_override_rx_mode()
305 	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);  in cphy_override_rx_mode()
307 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
310 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
314 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
317 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
320 	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);  in cphy_override_rx_mode()
325 static void highbank_cphy_override_lane(u8 sata_port)  in highbank_cphy_override_lane()  argument
327 	u8 lane = port_data[sata_port].lane_mapping;  in highbank_cphy_override_lane()
330 	if (unlikely(port_data[sata_port].phy_base == NULL))  in highbank_cphy_override_lane()
333 		tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +  in highbank_cphy_override_lane()
336 	cphy_override_rx_mode(sata_port, 3);  in highbank_cphy_override_lane()
337 	cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);  in highbank_cphy_override_lane()