Lines Matching refs:src
62 #define MAJOR_HW_REV_RD(src) (((src) & 0x0f000000) >> 24) argument
63 #define MINOR_HW_REV_RD(src) (((src) & 0x00f00000) >> 20) argument
64 #define HW_PATCH_LEVEL_RD(src) (((src) & 0x000f0000) >> 16) argument
65 #define MAX_REFILL_CYCLES_SET(dst, src) \ argument
66 ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
67 #define MIN_REFILL_CYCLES_SET(dst, src) \ argument
68 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
69 #define ALARM_THRESHOLD_SET(dst, src) \ argument
70 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
71 #define ENABLE_RNG_SET(dst, src) \ argument
72 ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
73 #define REGSPEC_TEST_MODE_SET(dst, src) \ argument
74 ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
75 #define MONOBIT_FAIL_MASK_SET(dst, src) \ argument
76 ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
77 #define POKER_FAIL_MASK_SET(dst, src) \ argument
78 ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
79 #define LONG_RUN_FAIL_MASK_SET(dst, src) \ argument
80 ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
81 #define RUN_FAIL_MASK_SET(dst, src) \ argument
82 ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
83 #define NOISE_FAIL_MASK_SET(dst, src) \ argument
84 ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
85 #define STUCK_OUT_MASK_SET(dst, src) \ argument
86 ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
87 #define SHUTDOWN_OFLO_MASK_SET(dst, src) \ argument
88 ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))