321 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))  macro
328 	write_reg(info, (reg), \
331 	write_reg(info, (reg), \
358 	{ info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
361 	{ info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
701 	write_reg(info, (unsigned char) (channel + CMDR), cmd);  in issue_command()
1025 			write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));  in tx_ready()
1888 	write_reg(info, PVR, val);  in set_interface()
2930 		write_reg(info, (unsigned char) (channel + BGR),  in mgslpc_set_rate()
2934 		write_reg(info, (unsigned char) (channel + CCR2), val);  in mgslpc_set_rate()
2961 	write_reg(info, CHB + MODE, val);  in enable_auxclk()
2973 	write_reg(info, CHB + CCR0, 0xc0);  in enable_auxclk()
2986 	write_reg(info, CHB + CCR1, 0x17);  in enable_auxclk()
3001 		write_reg(info, CHB + CCR2, 0x38);  in enable_auxclk()
3003 		write_reg(info, CHB + CCR2, 0x30);  in enable_auxclk()
3016 	write_reg(info, CHB + CCR4, 0x50);  in enable_auxclk()
3033 	write_reg(info, CHA + CCR1, val);  in loopback_enable()
3037 	write_reg(info, CHA + CCR2, val);  in loopback_enable()
3047 	write_reg(info, CHA + MODE, val);  in loopback_enable()
3104 	write_reg(info, CHA + MODE, val);  in hdlc_mode()
3132 	write_reg(info, CHA + CCR0, val);  in hdlc_mode()
3146 	write_reg(info, CHA + CCR1, val);  in hdlc_mode()
3170 	write_reg(info, CHA + CCR2, val);  in hdlc_mode()
3201 	write_reg(info, CHA + CCR3, val);  in hdlc_mode()
3212 	write_reg(info, CHA + PRE, val);  in hdlc_mode()
3226 	write_reg(info, CHA + CCR4, val);  in hdlc_mode()
3237 	write_reg(info, CHA + RLCR, 0);  in hdlc_mode()
3252 	write_reg(info, CHA + XBCH, val);  in hdlc_mode()
3374 	write_reg(info, CHA + CCR0, 0x80);  in reset_device()
3375 	write_reg(info, CHB + CCR0, 0x80);  in reset_device()
3376 	write_reg(info, CHA + MODE, 0);  in reset_device()
3377 	write_reg(info, CHB + MODE, 0);  in reset_device()
3394 	write_reg(info, PCR, 0x06);  in reset_device()
3418 	write_reg(info, IPC, 0x05);  in reset_device()
3450 	write_reg(info, CHA + MODE, val);  in async_mode()
3462 	write_reg(info, CHA + CCR0, 0x83);  in async_mode()
3473 	write_reg(info, CHA + CCR1, 0x1f);  in async_mode()
3487 	write_reg(info, CHA + CCR2, 0x10);  in async_mode()
3496 	write_reg(info, CHA + CCR3, 0);  in async_mode()
3508 	write_reg(info, CHA + CCR4, 0x50);  in async_mode()
3534 	write_reg(info, CHA + DAFO, val);  in async_mode()
3548 	write_reg(info, CHA + RFC, 0x5c);  in async_mode()
3554 	write_reg(info, CHA + RLCR, 0);  in async_mode()
3569 	write_reg(info, CHA + XBCH, val);  in async_mode()
3641 	write_reg(info, CHA + MODE, val);  in set_signals()
3765 		write_reg(info, XAD1, patterns[i]);  in register_test()
3766 		write_reg(info, XAD2, patterns[(i + 1) % count]);  in register_test()
3794 	write_reg(info, CHA + TIMR, 0);	/* 512 cycles */  in irq_test()