441 	u16 clk_val;  member
501 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_unprepare()
516 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_enable()
519 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);  in syscon_clk_enable()
530 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_disable()
533 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_disable()
536 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);  in syscon_clk_disable()
570 	switch(sclk->clk_val) {  in syscon_clk_recalc_rate()
637 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_round_rate()
656 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_set_rate()
697 		    u16 clk_val)  in syscon_clk_register()  argument
722 	sclk->clk_val = clk_val;  in syscon_clk_register()
746 	u16 clk_val;  member
754 		.clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
760 		.clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
766 		.clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
772 		.clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
778 		.clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
784 		.clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
790 		.clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
797 		.clk_val = 0xFFFFU,
803 		.clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
809 		.clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
815 		.clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
821 		.clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
827 		.clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
833 		.clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
839 		.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
845 		.clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
852 		.clk_val = 0xFFFFU,
858 		.clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
864 		.clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
918 						  u3clk->clk_val);  in of_u300_syscon_clk_init()