66 	u8              muxsel;  member
85 	u32 regval = readl(mux->feedback_reg[mux->muxsel]);  in clkgena_divmux_is_running()
99 	ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);  in clkgena_divmux_enable()
141 	genamux->muxsel = clk_mux_ops.get_parent(mux_hw);  in clkgena_divmux_get_parent()
142 	if ((s8)genamux->muxsel < 0) {  in clkgena_divmux_get_parent()
145 		genamux->muxsel = 0;  in clkgena_divmux_get_parent()
148 	return genamux->muxsel;  in clkgena_divmux_get_parent()
158 	genamux->muxsel = index;  in clkgena_divmux_set_parent()
175 	struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;  in clkgena_divmux_recalc_rate()
186 	struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;  in clkgena_divmux_set_rate()
197 	struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;  in clkgena_divmux_round_rate()