124 static void __iomem *clk_base;  variable
1022 static void tegra124_utmi_param_configure(void __iomem *clk_base)  in tegra124_utmi_param_configure()  argument
1038 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);  in tegra124_utmi_param_configure()
1055 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);  in tegra124_utmi_param_configure()
1058 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1073 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1076 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1080 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1082 	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1085 	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);  in tegra124_utmi_param_configure()
1091 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1094 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1099 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1101 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra124_utmi_param_configure()
1104 static __init void tegra124_periph_clk_init(void __iomem *clk_base,  in tegra124_periph_clk_init()  argument
1117 			       clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);  in tegra124_periph_clk_init()
1123 			       clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);  in tegra124_periph_clk_init()
1129 			       clk_base + CLK_SOURCE_EMC,  in tegra124_periph_clk_init()
1133 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1139 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra124_periph_clk_init()
1144 	tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);  in tegra124_periph_clk_init()
1147 static void __init tegra124_pll_init(void __iomem *clk_base,  in tegra124_pll_init()  argument
1154 	clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,  in tegra124_pll_init()
1161 			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1164 				clk_base + PLLC_OUT, 1, 0,  in tegra124_pll_init()
1176 	clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1182 	clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1188 	clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1196 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra124_pll_init()
1199 				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra124_pll_init()
1211 	val = readl(clk_base + pll_u_params.base_reg);  in tegra124_pll_init()
1213 	writel(val, clk_base + pll_u_params.base_reg);  in tegra124_pll_init()
1215 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1220 	tegra124_utmi_param_configure(clk_base);  in tegra124_pll_init()
1224 				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,  in tegra124_pll_init()
1248 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,  in tegra124_pll_init()
1260 	clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,  in tegra124_pll_init()
1266 					 clk_base + PLLRE_BASE, 16, 4, 0,  in tegra124_pll_init()
1273 				      clk_base, 0, &pll_e_params, NULL);  in tegra124_pll_init()
1278 	clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1284 	clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1290 	clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,  in tegra124_pll_init()
1309 		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);  in tegra124_wait_cpu_in_reset()
1324 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1325 	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_suspend()
1331 				clk_base + CLK_SOURCE_CSITE);  in tegra124_cpu_clock_resume()
1401 	clk_base = of_iomap(np, 0);  in tegra124_clock_init()
1402 	if (!clk_base) {  in tegra124_clock_init()
1421 	clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);  in tegra124_clock_init()
1425 	if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,  in tegra124_clock_init()
1430 	tegra124_pll_init(clk_base, pmc_base);  in tegra124_clock_init()
1431 	tegra124_periph_clk_init(clk_base, pmc_base);  in tegra124_clock_init()
1432 	tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);  in tegra124_clock_init()
1435 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,  in tegra124_clock_init()