Lines Matching refs:clk_base
140 static void __iomem *clk_base; variable
583 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
617 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
639 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
645 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
648 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
653 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
660 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
663 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra20_pll_init()
668 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
673 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
678 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
688 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, in tegra20_pll_init()
694 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
697 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra20_pll_init()
702 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
721 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); in tegra20_super_clk_init()
727 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); in tegra20_super_clk_init()
747 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); in tegra20_audio_clk_init()
749 clk_base + AUDIO_SYNC_CLK, 4, in tegra20_audio_clk_init()
757 TEGRA_PERIPH_NO_RESET, clk_base, in tegra20_audio_clk_init()
809 clk_base, 0, 3, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
813 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, in tegra20_periph_clk_init()
821 clk_base + CLK_SOURCE_EMC, in tegra20_periph_clk_init()
823 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, in tegra20_periph_clk_init()
828 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, in tegra20_periph_clk_init()
834 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, in tegra20_periph_clk_init()
842 clk_base, 0, 94, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
849 clk_base, 0, 93, periph_clk_enb_refcnt); in tegra20_periph_clk_init()
856 clk_base, data->offset, data->flags); in tegra20_periph_clk_init()
865 clk_base, data->offset); in tegra20_periph_clk_init()
869 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); in tegra20_periph_clk_init()
898 reg = readl(clk_base + in tegra20_wait_cpu_in_reset()
909 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); in tegra20_put_cpu_in_reset()
916 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); in tegra20_cpu_out_of_reset()
924 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
926 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
928 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_enable_cpu_clock()
935 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_disable_cpu_clock()
937 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra20_disable_cpu_clock()
945 cpu_rst_status = readl(clk_base + in tegra20_cpu_rail_off_ready()
955 readl(clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()
956 writel(3<<30, clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()
959 readl(clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_suspend()
961 readl(clk_base + PLLX_BASE); in tegra20_cpu_clock_suspend()
963 readl(clk_base + PLLX_MISC); in tegra20_cpu_clock_suspend()
965 readl(clk_base + SUPER_CCLK_DIVIDER); in tegra20_cpu_clock_suspend()
973 reg = readl(clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_resume()
986 clk_base + PLLX_MISC); in tegra20_cpu_clock_resume()
988 clk_base + PLLX_BASE); in tegra20_cpu_clock_resume()
1000 clk_base + SUPER_CCLK_DIVIDER); in tegra20_cpu_clock_resume()
1002 clk_base + CCLK_BURST_POLICY); in tegra20_cpu_clock_resume()
1005 clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_resume()
1090 clk_base = of_iomap(np, 0); in tegra20_clock_init()
1091 if (!clk_base) { in tegra20_clock_init()
1108 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, in tegra20_clock_init()
1117 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); in tegra20_clock_init()