28 static inline u32 qce_read(struct qce_device *qce, u32 offset)  in qce_read()  argument
30 	return readl(qce->base + offset);  in qce_read()
33 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)  in qce_write()  argument
35 	writel(val, qce->base + offset);  in qce_write()
38 static inline void qce_write_array(struct qce_device *qce, u32 offset,  in qce_write_array()  argument
44 		qce_write(qce, offset + i * sizeof(u32), val[i]);  in qce_write_array()
48 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)  in qce_clear_array()  argument
53 		qce_write(qce, offset + i * sizeof(u32), 0);  in qce_clear_array()
148 static u32 qce_config_reg(struct qce_device *qce, int little)  in qce_config_reg()  argument
150 	u32 beats = (qce->burst_size >> 3) - 1;  in qce_config_reg()
151 	u32 pipe_pair = qce->pipe_pair_id;  in qce_config_reg()
197 static void qce_xtskey(struct qce_device *qce, const u8 *enckey,  in qce_xtskey()  argument
206 	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);  in qce_xtskey()
210 	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);  in qce_xtskey()
213 static void qce_setup_config(struct qce_device *qce)  in qce_setup_config()  argument
218 	config = qce_config_reg(qce, 0);  in qce_setup_config()
221 	qce_write(qce, REG_STATUS, 0);  in qce_setup_config()
222 	qce_write(qce, REG_CONFIG, config);  in qce_setup_config()
225 static inline void qce_crypto_go(struct qce_device *qce)  in qce_crypto_go()  argument
227 	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));  in qce_crypto_go()
237 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_ahash()  local
249 	qce_setup_config(qce);  in qce_setup_regs_ahash()
252 		qce_write(qce, REG_AUTH_SEG_CFG, 0);  in qce_setup_regs_ahash()
253 		qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
254 		qce_write(qce, REG_ENCR_SEG_SIZE, 0);  in qce_setup_regs_ahash()
255 		qce_clear_array(qce, REG_AUTH_IV0, 16);  in qce_setup_regs_ahash()
256 		qce_clear_array(qce, REG_AUTH_KEY0, 16);  in qce_setup_regs_ahash()
257 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
266 		qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,  in qce_setup_regs_ahash()
279 	qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);  in qce_setup_regs_ahash()
282 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
284 		qce_write_array(qce, REG_AUTH_BYTECNT0,  in qce_setup_regs_ahash()
300 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_ahash()
301 	qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
302 	qce_write(qce, REG_AUTH_SEG_START, 0);  in qce_setup_regs_ahash()
303 	qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
304 	qce_write(qce, REG_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
307 	config = qce_config_reg(qce, 1);  in qce_setup_regs_ahash()
308 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_ahash()
310 	qce_crypto_go(qce);  in qce_setup_regs_ahash()
322 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_ablkcipher()  local
331 	qce_setup_config(qce);  in qce_setup_regs_ablkcipher()
341 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_ablkcipher()
353 			qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,  in qce_setup_regs_ablkcipher()
360 	qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);  in qce_setup_regs_ablkcipher()
368 		qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);  in qce_setup_regs_ablkcipher()
374 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);  in qce_setup_regs_ablkcipher()
375 	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);  in qce_setup_regs_ablkcipher()
376 	qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);  in qce_setup_regs_ablkcipher()
379 		qce_write(qce, REG_CNTR_MASK, ~0);  in qce_setup_regs_ablkcipher()
380 		qce_write(qce, REG_CNTR_MASK0, ~0);  in qce_setup_regs_ablkcipher()
381 		qce_write(qce, REG_CNTR_MASK1, ~0);  in qce_setup_regs_ablkcipher()
382 		qce_write(qce, REG_CNTR_MASK2, ~0);  in qce_setup_regs_ablkcipher()
385 	qce_write(qce, REG_SEG_SIZE, totallen);  in qce_setup_regs_ablkcipher()
388 	config = qce_config_reg(qce, 1);  in qce_setup_regs_ablkcipher()
389 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_ablkcipher()
391 	qce_crypto_go(qce);  in qce_setup_regs_ablkcipher()
412 int qce_check_status(struct qce_device *qce, u32 *status)  in qce_check_status()  argument
416 	*status = qce_read(qce, REG_STATUS);  in qce_check_status()
430 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)  in qce_get_version()  argument
434 	val = qce_read(qce, REG_VERSION);  in qce_get_version()